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preliminary product information this document contains information for a new product. cirrus logic reserves the right to modify this product without notice. 1 copyright ? cirrus logic, inc. 2000 (all rights reserved) p.o. box 17847, austin, texas 78760 (512) 445 7222 fax: (512) 445 7581 http://www.cirrus.com features l dual t1/e1 line interface l 3.3 volt and 5 volt versions l crystal- less jitter attenuator meets european ctr 12 and etsi ets 300 011 specifications l matched impedance transmit drivers l transmitter tri - state capability l common transmit and receivetransformers for all modes l serial and parallel host mode operation l user- c ustomizable pulse shapes l supports jtag boundary scan l compliant with: C itu-t recommendations: g.703, g.704, g.706, g.732, g.775 and i.431 C american national standards (ansi): t1.102, t1.105, t1.403, t1.408, and t1.231 C fcc rules and regulations: part 68 and part 15 C at&t publication 62411 C etsi ets 300 011, 300 233, ctr 12, tbr 13 l tr-net-00499 description the cs61584a is a dual line interface for t1/e1 appli- cations, designed for high-volume cards where low power and high density are required. the device is op- timized for flexible microprocessor control through a serial or parallel host mode interface. hardware mode operation is also available. matched impedance drivers reduce power consumption and provide substantial transmitter return loss. the transmitter pulse shapes are customizable to allow non- standard line loads. crystalless jitter attenuation com- plies with most stringent standards. support of jtag boundary scan enhances system testability and reliability. ordering information see page 53. cs61584a-iq3:3.3v, 64-pin tqfp, -40 to +85 c cs61584a-il5:5.0v, 68-pin plcc, -40 to +85 c cs61584a-iq5:5.0v, 64-pin tqfp, -40 to +85 c ttip1 tring1 rring1 rtip1 driver control tclk1 rclk1 reset jtag 4 refclk xtalout 1xclk tv+ tgnd rv+ rgnd dv+ dgnd clock generator serial port parallel port hardware mode int int rloop1 sclk rd(ds) rloop2 sdo ad0 lloop sdi ad1 taos1 ad3 con01 ad4 con02 ad5 con11 ad6 con12 ad7 con21 ale(as) con22 bts con32 (tdata1) tpos1 (ais1) tneg1 (rdata1) rpos1 (bpv1) rneg1 l o c a l l o o p b a c k 2 av+ agnd bgref mode wr(r/w) con31 spol ad2 taos2 pd1 sad4 ztx1 pd2 sad5 ztx2 los1 sad6 los1 los2 sad7 los2 pulse shaping circuitry clock & data recovery los & ais detect jitter attenuator p/s p/s atten0 cs cs atten1 taos e n c o d e r d e c o d e r control hardware mode parallel port serial port l o c a l l o o p b a c k 1 r e m o t e l o o p b a c k ttip2 tring2 rring2 rtip2 driver tclk2 rclk2 (tdata2) tpos2 (ais2) tneg2 (rdata2) rpos2 (bpv2) rneg2 l o c a l l o o p b a c k 2 pulse shaping circuitry clock & data recovery los & ais detect jitter attenuator taos e n c o d e r d e c o d e r l o c a l l o o p b a c k 1 r e m o t e l o o p b a c k 2 2 2 2 3 receiver receiver ipol (dtack) clke ipol dual t1/e1 line interface jan 01 ds261pp5 cs61584a copyright ? cirrus logic, inc. 2005 (all rights reserved) http://www.cirrus.com cs61584a dual t1/e1 line interface sep ?05 ds261f1
cs61584a 2 ds261pp5 ds261pp5 table of contents 1. characteristics and specifications ........................................................................ 5 absolute maximum ratings ........................................................................................... 5 recommended operating conditions ....................................................................... 5 analog characteristics ................................................................................................ 6 analog characteristics ................................................................................................ 7 digital characteristics ................................................................................................. 8 switching characteristics .......................................................................................... 8 switching characteristics - serial port ............................................................. 10 switching characteristics - parallel port ........................................................ 11 switching characteristics - jtag ............................................................................ 14 2. overview .................................................................................................................. ........... 15 2.1 at&t 62411 customer premises application .................................................................. 16 2.2 asynchronous multiplexer application ............................................................................. 16 2.3 synchronous application ................................................................................................. 16 3. transmitter ............................................................................................................... ........ 16 4. receiver .................................................................................................................. ............ 18 5. jitter attenuator ......................................................................................................... .19 6. reference clock ........................................................................................................... .20 7. power-up reset ............................................................................................................ .... 20 8. line control and monitoring .................................................................................... 20 8.1 line code encoder/decoder ............................................................................................ 20 8.2 alarm indication signal ................................................................................................... .20 8.3 bipolar violation detection ............................................................................................... 21 8.4 excessive zeros detection .............................................................................................. 21 8.5 loss of signal ............................................................................................................ ...... 21 8.6 transmit all ones ......................................................................................................... ... 21 8.7 receive all ones .......................................................................................................... ... 21 8.8 local loopback ............................................................................................................ .... 22 8.9 remote loopback ........................................................................................................... .22 8.10 driver tristate .......................................................................................................... ...... 22 8.11 power down ............................................................................................................... .... 22 8.12 reset pin ................................................................................................................ ....... 23 9. host mode ................................................................................................................. .......... 23 9.1 register set .............................................................................................................. ....... 23 9.1.1 status registers .................................................................................................. 23 contacting cirrus logic support for a complete listing of direct sales, distributor, and sales representative contacts, visit the cirrus logic web site at: http://www.cirrus.com/corporate/contacts/sales.cfm preliminary product information describes products which are in production, but for which full characterization data is not yet available. advance product infor- mation describes products which are in development and subject to development changes. cirrus logic, inc. has made best effort s to ensure that the information contained in this document is accurate and reliable. however, the information is subject to change without notice and is provi d ed as is without warranty of any kind (express or implied). customers are advised to obtain the latest version of relevant information to verify, before pla cing orders, that information being relied on is current and complete. all products are sold subject to the terms and conditions of sale supplied at the time of o rder acknowledgment, including those pertaining to warranty, patent infringement, and limitation of liability. no responsibility is assumed by cirrus logic, inc. f or the use of this information, including use of this information as the basis for manufacture or sale of any items, nor for infringements of patents or other rights of third parties. this document is the property of cirrus logic, inc. and by furnishing this information, cirrus logic, inc. grants no license, express or implied un der any patents, mask work rights, copyrights, trademarks, trade secrets or other intellectual property rights of cirrus logic, inc. cirrus logic, inc., copyrigh t owner of the information contained herein, gives consent for copies to be made of the information only for use within your organization with respect to cirrus log ic integrated circuits or other parts of cirrus logic, inc. the same consent is given for similar information contained on any cirrus logic website or disk. this c onsent does not extend to other copying such as copying for general distribution, advertising or promotional purposes, or for creating any work for resale. the names of products of cirrus logic, inc. or other vendors and suppliers appearing in this document may be trademarks or service marks of their respective owners wh ich may be registered in some jurisdictions. a list of cirrus logic, inc. trademarks and service marks can be found at http://www.cirrus.com . cs61584a 2 ds261f1
cs61584a ds261pp5 3 ds261pp5 9.1.2 mask registers ................................................................................................... 25 9.1.3 control a registers ............................................................................................. 26 9.1.4 control b registers ............................................................................................. 27 9.1.5 arbitrary waveform registers ............................................................................. 27 9.2 serial port operation ..................................................................................................... .. 30 9.3 parallel port operation ................................................................................................... .31 10. jtag boundary scan .................................................................................................... 31 10.1 jtag data registers (dr) ............................................................................................ 32 10.2 jtag instructions and instruction register (ir) ............................................................ 33 10.3 jtag tap controller ..................................................................................................... 3 3 10.4 test-logic-reset state .................................................................................................. 3 3 10.5 run-test/idle state ...................................................................................................... .. 34 10.6 select-dr-scan state ................................................................................................... 34 10.7 capture-dr state ......................................................................................................... .34 10.8 shift-dr state ........................................................................................................... ..... 34 10.9 exit1-dr state ........................................................................................................... .... 34 10.10 pause-dr state .......................................................................................................... .35 10.11 exit2-dr state .......................................................................................................... ... 35 10.12 update-dr state ......................................................................................................... 35 10.13 select-ir-scan state ................................................................................................... 3 5 10.14 capture-ir state ........................................................................................................ .. 35 10.15 shift-ir state .......................................................................................................... ..... 35 10.16 exit1-ir state .......................................................................................................... .... 36 10.17 pause-ir state .......................................................................................................... .. 36 10.18 exit2-ir state .......................................................................................................... .... 36 10.19 update-ir state ......................................................................................................... .. 36 10.20 jtag application examples ........................................................................................ 36 11. pin descriptions ......................................................................................................... ... 39 12. package dimensions .................................................................................................... 46 13. applications ............................................................................................................. ...... 48 13.1 line interface ........................................................................................................... ...... 48 13.2 power supply ............................................................................................................. ... 50 13.3 quartz crystal specifications ........................................................................................ 50 13.4 crystal oscillator specifications .................................................................................... 50 13.5 transformers ............................................................................................................. .... 51 13.6 designing for at&t 62411 ............................................................................................ 51 13.7 line protection .......................................................................................................... ..... 51 13.8 loop selection equations .............................................................................................. 51 list of tables table 1. line configuration selections......................................................................................... .... 17 table 3. jitter attenuation control............................................................................................ ........ 19 table 4. cs61584a register set ................................................................................................. .... 23 table 5. status registers ...................................................................................................... ........... 24 table 6. mask registers........................................................................................................ ........... 25 table 7. control a registers ................................................................................................... ......... 26 table 8. control b registers ................................................................................................... ......... 27 table 9. arbitrary waveform registers .......................................................................................... .. 28 table 10. boundary scan register ............................................................................................... ... 32 table 11. device identifcation register........................................................................................ .... 33 table 12. ..................................................................................................................... .................... 33 cs61584a ds261f1 3
cs61584a 4 ds261pp5 ds261pp5 table 13. cs61584a external components..................................................................................... 48 table 14. quartz crystal specifications ........................................................................................ ... 50 table 15. suggested quartz crystals............................................................................................ ... 50 table 16. suggested crystal oscillators ........................................................................................ .. 50 table 17. transformer specifications ........................................................................................... .... 51 table 18. recommended transformers........................................................................................... 52 list of figures figure 1. signal rise and fall characteristics .............................................................................. 9 figure 2. recovered clock and data switching characteristics ................................................... 9 figure 3. transmit clock and data switching characteristics ...................................................... 9 figure 4. serial port write timing diagram ................................................................................. 10 figure 5. serial port read timing diagram ................................................................................ 10 figure 6. parallel port timing - motorola mode ........................................................................... 12 figure 7. parallel port timing - intel read mode ........................................................................ 12 figure 8. parallel port timing - intel write mode ........................................................................ 12 figure 9. parallel port timing - motorola mode to ram .............................................................. 13 figure 10. parallel port timing - intel read mode from ram or rom ......................................... 13 figure 11. parallel port timing - intel write mode to ram ........................................................... 13 figure 12. jtag switching characteristics ................................................................................... 14 figure 13. examples of cs61584a applications ........................................................................... 15 figure 14. typical pulse shape at dsx-1 cross connect ............................................................ 17 figure 15. mask of the pulse at the 2048 kbps interface .............................................................. 17 figure 16. minimum input jitter tolerance of receiver (clock recovery circuit and jitter attenuator) ............................................................................................................ 18 figure 17. typical jitter transfer function .................................................................................... 19 figure 18. alarm indication event relationships ........................................................................... 24 figure 19. phase definition of arbitrary waveforms ..................................................................... 29 figure 20. example of summing of waveforms ............................................................................ 29 figure 21. serial read/write format (spol = 0) .......................................................................... 30 figure 22. address command byte ............................................................................................... 3 0 figure 23. jtag circuitry block diagram ..................................................................................... 31 figure 24. tap controller state diagram ...................................................................................... 34 figure 25. jtag instruction register update ................................................................................ 37 figure 26. jtag data register update ......................................................................................... 38 figure 27. hardware mode configuration ..................................................................................... 48 figure 28. host mode serial port configuration ............................................................................ 49 figure 29. host mode parallel port configuration ......................................................................... 49 cs61584a 4 ds261f1
cs61584a ds261pp5 5 ds261pp5 1. characteristics and specifications absolute maximum ratings notes: 1. referenced to rgnd1, rgnd2, tgnd1, tgnd2, agnd, dgnd at 0 v. 2. transient currents of up to 100 ma will not cause scr latch-up. warning: operation at or beyond these limits may result in permanent damage to the device. normal operation is not guaranteed at these extremes. recommended operating conditions notes: 3. tv+1, tv+2, av+, dv+, rv+1, rv+2 should be connected together. tgnd1, tgnd2, rgnd1, gnd2, dgnd1, dgnd2, dgnd3 should be connected together. 4. per channel power consumption while driving line load over operating temperature range. includes device and load. digital input levels are within 10% of the supply rails and digital outputs are driving a 50 pf capacitive load. 5. assumes 100% ones density and maximum line length at maximum supply voltage (3.465 v or 5.25 v). 6. assumes 50% ones density and 300 ft. line length at typical supply voltage (3.3 v or 5.0 v). specifications are subject to change without notice parameter symbol min max unit dc supply (tv+1, tv+2, rv+1, rv+2, av+, dv+) (note 1) - 6.0 v input voltage (any pin) v in rgnd - 0.3 (rv+) + 0.3 v input current (any pin) (note 2) i in -10 10 ma ambient operating temperature t a -40 85 c storage temperature t stg -65 150 c parameter symbol min typ max unit dc supply (tv+1, tv+2, rv+1, rv+2, av+, dv+) (note 3) 3.3 v 5.0 v 3.135 4.75 3.3 5.0 3.465 5.25 v ambient operating temperature t a -40 25 85 c power consumption per channel (3.3 v) (note 4) t1 (note 5) t1 (note 6) e1, 75 w (note 5) e1, 120 w (note 5) p c - - - - 310 190 250 230 - - - - mw power consumption per channel (5.0 v) (note 4) t1 (note 5) t1 (note 6) e1, 75 w (note 5) e1, 120 w (note 5) p c - - - - 350 250 320 310 - - - - mw refclk frequency t1 1xclk = 1 t1 1xclk = 0 (1.544 - 100 ppm) (12.352 - 100 ppm) 1.544 12.352 (1.544 + 100 ppm) (12.352 + 100 ppm) mhz mhz refclk frequency e1 1xclk = 1 e1 1xclk = 0 (2.048 - 100 ppm) (16.384 - 100 ppm) 2.048 16.384 (2.048 + 100 ppm) (16.384 + 100 ppm) mhz mhz cs61584a ds261f1 5
cs61584a 6 ds261pp5 ds261pp5 analog characteristics (t a = -40 to 85 c; power supply pins within 5% of nominal.) notes: 7. for input amplitude of 1.2 v pk to 4.14 v pk . 8. for input amplitude of 0.5 v pk to 1.2 v pk , and 4.14 v pk to 5.0 v pk . 9. for input amplitude of 1.07 v pk to 4.14 v pk . 10. for input amplitude of 4.14 v pk to 5.0 v pk . 11. jitter tolerance increases at lower frequencies. refer to the receiver section. 12. not production tested. parameters guaranteed by design and characterization. 13. typical performance using the line interface circuitry recommended in the applications section. 14. return loss = 20 log 10 abs((z 1 + z 0 ) / (z 1 - z 0 )) where z 1 = impedance of the transmitter or receiver, and z 0 = cable impedance. 15. attenuation measured with sinusoidal input jitter equal to 3/4 of measured jitter tolerance. circuit attenuates jitter at 20 db/decade above the corner frequency. output jitter can increase significantly when more than 28 ui's are input to the attenuator. the jitter attenuator -3 db knee in t1 mode is selectable for 4.0 hz or 1.25 hz. refer to the jitter attenuator section. parameter symbol min typ max unit receiver rtip/rring differential input impedance - 20 - k w sensitivity below dsx-1 (0 db = 2.4 v) - -13.6 - db loss of signal threshold - 0.3 - v data decision threshold t1, dsx-1 (note 7) (note 8) t1, fcc part 68 and e1 (note 9) (note 10) 60 55 45 40 65 - 50 - 70 75 55 60 % of peak allowable consecutive zeros before los 160 175 190 bits receiver input jitter tolerance (dsx-1, e1) 10 hz and below (note 11) 2khz 10 khz - 100 khz 300 6.0 0.4 - - - - - - ui receiver return loss (notes 12, 13, and 14) 51 khz - 102 khz 102 khz - 2.048 mhz 2.048 mhz - 3.072 mhz 12 18 14 22 24 22 - - - db jitter attenuator jitter attenuator corner frequency t1 (notes 12 and 15) e1 1.25 - 4.0 1.25 - - hz attenuation at 10 khz jitter frequency (notes 12 and 15) - 60 - db attenuator input jitter tolerance (note 12) (before onset of fifo overflow or underflow protection) 28 43 - ui pk-pk transmitter arbitrary pulse amplitude at transformer secondary t1, dsx-1 t1, ds1 e1, 75 w e1, 120 w - - - - 73 52 43 52 - - - - mv/ls b cs61584a 6 ds261f1
cs61584a ds261pp5 7 ds261pp5 analog characteristics (continued) notes: 16. using a transformer that meets the specifications in the applications section. 17. measured across 75 w at the output of the transmit transformer for con3/2/1/0 = 0/0/0/0. 18. measured across 120 w at the output of the transmit transformer for con3/2/1/0 = 0/0/0/1. 19. measured at the dsx-1 cross-connect for line length settings con3/2/1/0 = 0/0/1/0, 0/0/1/1, 0/1/0/0, 0/1/0/1, and 0/1/1/0 after the length of #22 abam cable specified in table 1. 20. input signal to rtip/rring is jitter free. values will reduce slightly if jitter free clock is input to tclk. 21. transformer secondary shorted with 0.5 w resistor during the transmission of 100% ones. 22. at transformer secondary and measured from 10% to 90% of amplitude. parameter symbol min typ max unit transmitter (continued) ami output pulse amplitudes (note 16) e1, 75 w (note 17) e1, 120 w (note 18) t1, dsx-1 (note 19) 2.14 2.7 2.4 2.37 3.0 3.0 2.6 3.3 3.6 v recommended transmitter output load (3.3 v) (note 16) t1 e1, 75 w e1, 120 w - - - 24.8 18.6 30.0 - - - w recommended transmitter output load (5.0 v) (note 16) t1 e1, 75 w e1, 120 w - - - 76.6 57.4 90.6 - - - w jitter added during remote loopback 10 hz - 8 khz 8khz - 40khz 10 hz - 40 khz broad band (note 20) - - - - 0.020 0.015 0.015 0.045 - - - - ui power in 2 khz band about 772 khz (notes 12 and 13) (dsx-1 only) 12.6 15 17.9 dbm power in 2 khz band about 1.544 mhz (note 12 and 13) (referenced to power in 2 khz band at 772 khz, dsx-1 only) -29 -38 - db positive to negative pulse imbalance (notes 12 and 13) t1, dsx-1 e1, amplitude at center fo pulse interval e1, width at 50% of nominal amplitude - -5 -5 0.2 - - 0.5 5 5 db % % transmitter return loss (notes 12, 13, and 14) 51 khz - 102 khz 102 khz - 2.048 mhz 2.048 mhz - 3.072 mhz 8 14 10 25 18 12 - - - db e1 short circuit current 5.0 v (note 21) 3.3 v - - - 70 50 - ma rms ma rms e1 and dsx-1 output pulse rise/fall times (note 22) - 50 - ns e1 pulse width (at 50% of peak amplitude) - 244 - ns e1 pulse amplitude for a space e1, 75 w e1, 120 w -0.237 -0.3 - - 0.237 0.3 v v cs61584a ds261f1 7
cs61584a 8 ds261pp5 ds261pp5 digital characteristics (t a = -40 to 85 c; power supply pins within 5% of nominal.) notes: 23. digital inputs are designed for cmos logic levels. 24. digital outputs are ttl compatible and drive cmos levels into a cmos load. switching characteristics (t a = -40 to 85 c; power supply pins within 5% of nominal; inputs: logic 0 = 0 v, logic 1 = dv+.) notes: 25. the maximum burst rate of a gapped tclk input clock is 8.192 mhz. for the gapped clock to be tolerated by the cs61584a, the jitter attenuator must be switched to the transmit path of the line interface. the maximum gap size that can be tolerated on tclk is 28 uip-p. 26. rclk duty cycle may be outside the specified limits when the jitter attenuator is in the transmit path and when the jitter attenuator is employing the overflow/underflow protection mechanism. 27. at max load of 50 pf. parameter symbol min max unit high-level input voltage (note 23) v ih (dv+) - 0.5 - v low-level input voltage (note 23) v il -0.5v high-level output voltage (i out = -40 a) (note 24) v oh (dv+) - 0.3 - v low-level output voltage (i out = 1.6 ma) (note 24) v ol -0.3v input leakage current (digital pins except j-tms and j-tdi) - 10 a parameter symbol min typ max unit t1 clock/data tclk frequency (note 25) f tclk -1.544-mhz tclk duty cycle t pwh2 /t pw2 20 50 80 % rclk duty cycle (note 26) t pwh1 /t pw1 45 50 55 % rise time (all digital outputs) (note 27) t r - - 65 ns fall time (all digital outputs) (note 27) t f - - 65 ns rpos/rneg (rdata) to rclk rising setup time t su1 -274-ns rclk rising to rpos/rneg (rdata) hold time t h1 -274-ns tpos/tneg (tdata) to tclk falling setup time t su2 25 - - ns tclk falling to tpos/tneg (tdata) hold time t h2 25 - - ns e1 clock/data tclk frequency (note 25) f tclk -2.048-mhz tclk duty cycle t pwh2 /t pw2 20 50 80 % rclk duty cycle (note 26) t pwh1 /t pw1 45 50 55 % rise time (all digital outputs) (note 27) t r - - 65 ns fall time (all digital outputs) (note 27) t f - - 65 ns rpos/rneg (rdata) to rclk rising setup time t su1 -194-ns rclk rising to rpos/rneg (rdata) hold time t h1 -194-ns tpos/tneg (tdata) to tclk falling setup time t su2 25 - - ns tclk falling to tpos/tneg (tdata) hold time t h2 25 - - ns cs61584a 8 ds261f1
cs61584a ds261pp5 9 ds261pp5 any digital output t r t f 10% 10% 90% 90% figure 1. signal rise and fall characteristics rclk (for clke = high) rclk (for clke = low) rpos rneg rdata bpv t pw1 t pwl1 su1 t h1 t t pwh1 figure 2. recovered clock and data switching characteristics tclk tpos tneg tdata t pwh2 t pw2 t su2 t h2 figure 3. transmit clock and data switching characteristics cs61584a ds261f1 9
cs61584a 10 ds261pp5 ds261pp5 switching characteristics - serial port (t a = -40 to 85 c; dv+, tv+, rv+ = nominal 0.3 v; inputs: logic 0 = 0 v, logic 1 = rv+) notes: 28. if spol = 0, then cs should return high no sooner than 20 ns after the 16 th rising edge of sclk during a serial port read. 29. output load capacitance = 50 pf. parameter symbol min typ max unit sdi to sclk setup time t dc 25 - - ns sclk to sdi hold time t cdh 25 - - ns sclk low time t cl 50 - - ns sclk high time t ch 50 - - ns sclk rise and fall time t r , t f - - 15 ns cs to sclk setup time t cc 20 - - ns sclk to cs hold time (note 28) t cch 20 - - ns cs inactive time t cwh 100 - - ns sdo valid to sclk (note 29) t cdv - - 50 ns cs to sdo high z t cdz -50-ns t dc t cc lsb lsb msb control byte data byte cs sclk sdi t ch t cwh t cch t cdh t cl t cdh figure 4. serial port write timing diagram high cs sclk sdo spol = 0 t cdz cdv t figure 5. serial port read timing diagram cs61584a 10 ds261f1
cs61584a ds261pp5 11 ds261pp5 switching characteristics - parallel port (t a = -40 to 85 c; tv+, rv+ = nominal 0.3 v; inputs: logic 0 = 0 v, logic 1 = rv+) parameter symbol min max unit cycle time t cyc 250 - ns pulse width, ds low or rd high pw el 150 - ns pulse width, ds high or rd low pw eh 150 - ns input rise/fall times t r , t f -30ns r/w hold time t rwh 10 - ns r/w setup time before ds high t rws 50 - ns cs setup time before ds, wr , or rd active t cs 50 - ns cs setup time before ds, wr , or rd active for ram/rom t csr 130 - ns cs hold time t ch 20 - ns read data hold time t dhr 10 80 ns write data hold time t dhw 5-ns muxed address valid to as or ale fall t asl 15 - ns muxed address hold time t ahl 10 - ns delay time ds, wr , or rd to as or ale rise t asd 25 - ns pulse width as or ale high 40 - ns delay time as or ale to ds, wr , or rd t ased 40 - ns output data delay time from ds or rd t ddr 20 120 ns data setup time t dsw 80 - ns dtack delay t dkd 5-ns dtack hold time t dkh 5-ns as/ale min low interval for ram/rom t aamir 50 - ns cs61584a ds261f1 11
cs61584a 12 ds261pp5 ds261pp5 pw ash t asd t ased pw eh t cyc t rws t rwh t asl t ddr t dhr t ahl t ahl t asl t cs t dsw t dhw t ch as ds r/w ad0-ad7 (read) cs ad0-ad7 (write) dtack (read and write) t dkd t dkh figure 6. parallel port timing - motorola mode ad0-ad7 cs t cyc pw ash t asd t asd t asl t ased pw el t ahl t ddr t dhr t ch t cs rd wr ale figure 7. parallel port timing - intel read mode ad0-ad7 cs t cyc pw ash t asd t asd t asl t ased pw el t ahl t dhw t ch t cs wr rd ale t dsw figure 8. parallel port timing - intel write mode cs61584a 12 ds261f1
cs61584a ds261pp5 13 ds261pp5 pw ash t asd t ased pw eh t cyc t rws t rwh t asl t ddr t dhr t ahl t ahl t asl t csr t dsw t dhw t ch as ds r/w ad0-ad7 (read) cs ad0-ad7 (write) dtack (read and write) t dkd t dkh pw ash t asl t asl ahl t ahl t t aamir figure 9. parallel port timing - motorola mode to ram ad0-ad7 cs t cyc pw ash t asd t asd t asl t ased pw el t ahl t dhr t ch rd wr ale t ahl t csr t asl t aamir pw ash t ddr figure 10. parallel port timing - intel read mode from ram or rom ad0-ad7 cs t cyc pw ash t asd t asd t asl t ased pw el t ahl t dhr t ch rd wr ale t ahl t csr t asl t aamir pw ash t dsw figure 11. parallel port timing - intel write mode to ram cs61584a ds261f1 13
cs61584a 14 ds261pp5 ds261pp5 switching characteristics - jtag (t a = -40 to 85 c; tv+, rv+ = nominal 0.3 v; inputs: logic 0 = 0 v, logic 1 = rv+) parameter symbol min max unit cycle time t cyc 200 - ns j-tms/j-tdi to j-tck rising setup time t su 50 - ns j-tck rising to j-tms/j-tdi hold time t h 50 - ns j-tck falling to j-tdo valid t dv -60ns j-tck j-tms j-tdi j-tdo t su t h t cyc t dv figure 12. jtag switching characteristics cs61584a 14 ds261f1
cs61584a ds261pp5 15 ds261pp5 2. overview the cs61584a is a dual line interface for t1/e1 applications, designed for high-volume cards where low power and high density are required. the device can be operated in either hardware mode using control pins or in host mode using an internal register set. one board design can support all t1/e1 short-haul modes by only changing com- ponent values in the receive and transmit paths (if refclk and tclk are connected externally). figure 13 illustrates applications of the cs61584a in various environments. the line driver generates waveforms compatible with e1 (ccitt g.703), t1 short haul (dsx-1) and t1 fcc part 68 option a (ds1). a single transformer turns ratio is used for all waveform types. the driver internally matches the impedance of the load, providing excellent return loss to insure superior t1/e1 pulse quality. an additional benefit of the internal impedance matching is a 50 percent reduction in power consumption compared to im- plementing return loss using external resistors that causes the transmitter to drive the equivalent of two line loads. asynchronous mux application (i.e., vt1.5 card for sonet or sdh mux) loop timed application synchronous application (including 62411 systems with multiple t1 lines) ttip tpos tneg rneg tring rpos rring rtip cs62180b framer jitter attenuator cs61584a line driver line receiver receive circuitry transmit circuitry rclk tclk refclk ttip tdata rdata tring line driver ami b8zs, hdb3, coder rring rtip mux cs61584a jitter attenuator refclk rclk tclk (gapped) ttip tpos tneg rneg tring rpos rring rtip cs62180b framer jitter attenuator cs61584a line driver line receiver rclk tclk refclk ais detect line receiver receive circuitry transmit circuitry receive circuitry transmit circuitry figure 13. examples of cs61584a applications cs61584a ds261f1 15
cs61584a 16 ds261pp5 ds261pp5 the line receiver contains all the necessary clock and data recovery circuits. the jitter attenuator meets at&t 62411 require- ments when using either a 1x or 8x reference clock supplied by either a quartz crystal, crystal os- cillator, or external reference at the refclk input pin. 2.1 at&t 62411 customer premises application the at&t 62411 specification applies to the t1 interface between the customer premises and the carrier, and must be implemented by the customer premises equipment in order to connect to the at&t network. in 62411 applications, the management of jitter is a very important design consideration. typically, the jitter attenuator is placed in the receive path of the cs61584a to reduce the jitter input to the system synchronizer. the jitter attenuated recovered clock is used as the input to the transmit clock to imple- ment a loop-timed system. a stratum 4 (32 ppm) quality clock or better should be input to refclk. note that any jitter present on the reference clock will not be filtered by the jitter attenuator. 2.2 asynchronous multiplexer application asynchronous multiplexers accept multiple t1/e1 lines (which are asynchronous to each other), and combine them into a higher speed transmission rate (e.g. m13 muxes and sonet muxes). in these sys- tems, the jitter attenuator is placed in the transmit path of the cs61584a to remove the gapped clock jitter input by the multiplexer to tclk. because the transmit clock is jittered, the reference clock to the cs61584a is provided by an external source operating at 1x or 8x the data rate. because t1/e1 framers are not usually required in asynchronous multiplexers, the b8zs/ami/hdb3 coders in the cs61584a are activated to provide data interfaces on tdata and rdata. 2.3 synchronous application a typical example of a synchronous application is a t1 card in a central office switch or a 0/1 digital cross-connect system. these systems place the jit- ter attenuator in the receive path to reduce the jitter presented to the system. a stratum 3 or better sys- tem clock is input to the cs61584a transmit and reference clocks. 3. transmitter the transmitter accepts data from a t1 or e1 sys- tem and outputs pulses of appropriate shape to the line. the transmit clock (tclk) and transmit data (tpos and tneg, or tdata) are supplied syn- chronously. data is sampled on the falling edge of the tclk input. during hardware mode operation, the configura- tion pins (con[3:0]) control transmitted pulse shapes, transmitter source impedance, receiver slicing level, and driver tristate as shown in table 1. during host mode operation, the configu- ration is established by the con[3:0] bits in the control b registers. typical output pulses are shown in figures 14 and 15. these pulse shapes are fully pre-defined by circuitry in the cs61584a, and are fully compliant with appropriate standards when used with our application guidelines in stan- dard installations. both channels must be operated at the same line rate (both t1 or both e1). host mode operation permits arbitrary transmit pulse shapes to be created and downloaded to the cs61584a. these custom pulse shapes can be used to compensate for waveform degradation caused by non-standard cables, transformers, or protection circuitry (refer to the arbitrary waveform regis- ters section). note that the pulse width for part 68 option a (324 ns) is narrower than the optimal pulse width for dsx-1 (350 ns). the cs61584a automatically adjusts the pulse width based on the configuration selection. cs61584a 16 ds261f1
cs61584a ds261pp5 17 ds261pp5 500 1.0 0.5 0 -0.5 0 250 750 1000 normalized amplitude ansi t1.102 specification cs61584a output pulse shape time (nanoseconds) figure 14. typical pulse shape at dsx-1 cross connect 269 ns 244 ns 194 ns 219 ns 488 ns nominal puls e 0 10 50 80 90 100 110 120 -10 -20 percent of nominal peak voltage g.703 specification figure 15. mask of the pulse at the 2048 kbps interface c o n 3 c o n 2 c o n 1 c o n 0 transmit pulse width at 50% amplitude transmit pulse shape receiver slicing level line code encoder / decoder 0000 244ns (50%) e1: square, 2.37 v into 75 w 50% ami/hdb3 1000 244ns (50%) arbitrary e1 wave into 75 w 50% ami/hdb3 0001 244ns (50%) e1: square, 2.37 v into 75 w 50% ami/hdb3 1001 244ns (50%) arbitrary e1 wave into 120 w 50% ami/hdb3 0010 350ns (54%) dsx-1: 0-133 ft. 65% ami/b8zs 0011 350ns (54%) dsx-1: 133-266 ft. 65% ami/b8zs 0100 350ns (54%) dsx-1: 266-399 ft. 65% ami/b8zs 0101 350ns (54%) dsx-1: 399-533 ft. 65% ami/b8zs 0110 350ns (54%) dsx-1: 533-655 ft. 65% ami/b8zs 1010 350ns (54%) arbitrary dsx-1 waveform 65% ami/b8zs 0111 324ns (50%) ds1: fcc part 68 option a with undershoot 65% ami/b8zs 1100 324ns (50%) ds1: fcc part 68 option a (0 db) 65% ami/b8zs 1011 324ns (50%) arbitrary ds1 waveform 65% ami/b8zs 1101 reserved 1110 transmit hi z tristate ttip/tring driver outputs 50% ami/hdb3 1111 transmit hi z tristate ttip/tring driver outputs 65% ami/b8zs table 1. line configuration selections cs61584a ds261f1 17
cs61584a 18 ds261pp5 ds261pp5 the transmitter impedance changes with the line length options in order to match the load imped- ance (75 w for e1 coax, 100 w for t1, 120 w for e1 shielded twisted pair), providing a minimum of 14 db return loss for t1 and e1 frequencies during the transmission of both marks and spaces. this improves signal quality by minimizing reflections from the transmitter. impedance matching also re- duces load power consumption by a factor of two when compared to the return loss achieved by using external resistors. the cs61584a driver will automatically detect an inactive tlck (i.e., no data clocked to the driver) or refclk input. when either of these conditions are detected the driver is forced to the tristate (high- impedance) condition. if the jitter attenuator is in the transmit path, the driver will tristate after 170 to 182 tclk clock cycles. if the attenuator is not in the transmit path, the driver will tristate after 4 to 12 tclk clock cycles. during host mode opera- tion, the clklost bit in the status register goes high to indicate when the driver is tristated due to the absence of tclk or refclk. the driver exits the tristate condition when four clock cycles are in- put to tclk. on power-up or reset, the driver is tristated until refclk is present and four clock cycles are input to tclk. in host mode the driver will have to be taken out of the tristate condition by writing the con[3:0]. the driver is not forced to the tristate condition during remote loopback if tclk is absent. when the transmit configuration established by con[3:0], taos, or lloop changes state, the transmitter stabilizes within 22 tclk bit periods. the transmitter takes longer to stabilize when rloop1 or rloop2 is selected because the tim- ing circuitry must adjust to the new frequency from rclk. when the transmitter transformer secondaries are shorted through a 0.5 w resistor, the transmitter will output a maximum of 50 ma-rms, as required by the european specification bs6450. this spec is met for 5.0 v operation only. 4. receiver the input signal is connected to the receiver through a step down transformer (1.15:1 for 5 v and 2:1 for 3.3 v). data and clock are extracted from the t1/e1 signal input to the line interface and to the system. the signal is detected differentially across the receive transformer and can be recov- ered over the entire range of short haul cable lengths. the transmit and receive transformer spec- ifications are identical and are presented in the ap- plications section. as shown in table 1, the receiver slicing level is set at 65% for ds1/dsx-1 short-haul and at 50% for all other applications. the clock recovery circuit is a second-order phase locked loop that can tolerate up to 0.4 ui of jitter from 10 khz to 100 khz without generating errors (figure 13). the clock and data recovery circuit is tolerant of long strings of consecutive zeros and will successfully recover a 1-in-175 jitter-free line input signal. recovered data at rpos and rneg (or rdata) is stable and may be sampled using the recovered clock rclk. during hardware mode operation, 10 1k 10k 1 100 100k 700 .1 1 10 100 .4 28 300 300 peak-to-peak jitter (unit intervals) jitter frequency (hz) cs61584a performance 138 at&t 62411 (1990 version) figure 16. minimum input jitter tolerance of receiver (clock recovery circuit and jitter attenuator) cs61584a 18 ds261f1
cs61584a ds261pp5 19 ds261pp5 the clke pin determines the clock polarity where the output data is stable and valid as shown in table 2. during host mode operation, the polarity is established by the clke bit in the control a reg- ister. when clke is low, rpos and rneg (or rdata) are valid on the rising edge of rclk. when clke is high, rpos and rneg (or rda- ta) are valid on the falling edge of rclk during host mode operation, the data at rpos and rneg (or rdata) may be forced to output an un- framed all-ones pattern by setting both the lloop1 and lloop2 bits in the control b regis- ter to "1". 5. jitter attenuator the jitter attenuator can be switched into either the receive or transmit paths. alternatively, it can also be removed from both paths to reduce the propaga- tion delay. figure 14 illustrates the typical jitter at- tenuation curves. during hardware mode operation, the location of the jitter attenuators for both channels is controlled by the atten0 and atten1 pins. during host mode operation, the location of the jitter attenua- tors are independent and are controlled by the at- ten[1:0] bits in the control a registers. table 3 shows how these pins are decoded. the attenuator consists of a 64-bit fifo, a narrow- band monolithic pll, and control logic. signal jit- ter is absorbed in the fifo which is designed to neither overflow nor underflow. if overflow or un- derflow is imminent, the jitter transfer function is altered to ensure that no bit-errors occur. under this condition, jitter gain may occur and external provi- sions may be required. the jitter attenuator will typically tolerate 43 uis before the overflow/un- derflow mechanism occurs. if the jitter attenuator has not had time to "lock" to the average incoming frequency (e.g. following a device reset) the atten- uator will tolerate a minimum of 22 uis before the overflow/underflow mechanism occurs. the jitter attenuator -3 db knee frequency is 4.0 hz for t1 mode and 1.25 hz for e1 mode as selected by the con[3:0] pins or register bits. a 1.25 hz knee for the e1 mode guarantees jitter attenuation compliance to european specifications ctr 12 and etsi ets 300 011. setting atten[1:0] = 11 will place the jitter attenuator in the receive path with a 1.25 hz knee for both t1 and e1 modes of opera- tion. for t1/e1 line cards used in high-speed mutiplex- ers (e.g., sonet and sdh), the jitter attenuator is typically used in the transmit path. the attenuator can accept a transmit clock with gaps 28 uis and a transmit clock burst rate of 8 mhz. clke data clock clock edge for valid data low rpos, rneg or rdata rclk rclk rising rising high rpos, rneg or rdata rclk rclk falling falling table 2. recovered data/clock options attenuation in db frequency in hz 10 20 30 40 50 60 1 10 100 1 k 10 k maximum attenuation limit 62411 requirements minimum attenuation limit measured performance t1 mode e1 mode 0 figure 17. typical jitter transfer function atten1 atten0 location of jitter attenuator 00 receiver 0 1 disabled 1 0 transmitter 1 1 receiver w/ 1.25 hz knee table 3. jitter attenuation control cs61584a ds261f1 19
cs61584a 20 ds261pp5 ds261pp5 6. reference clock the cs61584a requires a reference clock with a minimum accuracy of 100 ppm for t1 and e1 ap- plications. this clock can be either a 1x clock (i.e., 1.544 mhz or 2.048 mhz), or can be a 8x clock (i.e., 12.352 mhz or 16.384 mhz) as selected by the 1xclk pin. this clock may be supplied from internal system timing or a cmos crystal oscillator and input to the refclk pin. an 8x quartz crystal may be connected across the refclk and xta- lout pins and the 1xclk pin set low. the quartz crystal and cmos crystal oscillator specifications and are presented in the applications section. in systems with a jittered transmit clock, the refer- ence clock should not be tied to the transmit clock and a separate external quartz crystal or crystal os- cillator should drive the reference clock input. any jitter present on the reference clock will not be fil- tered by the jitter attenuator. 7. power-up reset on power-up, the device is held in a static state un- til the power supply achieves approximately 60% of the power supply voltage. when this threshold is crossed, the device waits another 10 ms to allow the power supply to reach operating voltage and then calibrates the transmit and receive circuitry. this initial calibration takes less than 20 ms but can oc- cur only if refclk and tclk are present. power-up reset initializes the control logic and reg- ister set and performs the same functions as the re- set pin. during host mode operation, a reset event is indicated by the latched-reset bit in the status register. 8. line control and monitoring line control and monitoring of the cs61584a may be implemented in either hardware or host mode. hardware mode is selected when the mode pin is set low and allows the device to be configured and monitored using control pins. host mode is select- ed when the mode pin is set high and allows the device to be configured and monitored using an in- ternal register set. the following controls and indications are avail- able in hardware mode: line length selection, re- ceive clock edge, jitter attenuator location, loss of signal, transmit all ones, local loopback, remote loopback, and power down. host mode operation offers several additional control options (refer to the host mode section). note: please refer to the loop selection equations in the applications section. 8.1 line code encoder/decoder hardware mode supports only transparent opera- tion to permit the line code to be encoded and de- coded by an external t1/e1 framing device. recovered data is output on the rneg and rpos pins in nrz format and transmitted data is input on the tneg and tpos pins. host mode supports transparent, ami, b8zs, or hdb3 line encoding and decoding for applications not using an external t1/e1 framer (i.e. multiplex- ers). the coder, ami-t, and ami-r bits in the control a registers select the coder mode for a giv- en channel. the selection of the transmit encoder is independent from the selection of the receive de- coder. when coder = 1, the transmit data is input to the encoder on tdata and the receive data is output from the decoder on rdata in nrz for- mat. 8.2 alarm indication signal during host mode operation, the alarm indication signal (ais) is detected by the receiver and report- ed using the ais and latched-ais bits in the status registers. the receiver detects the ais condition on observation of 99.9% ones density in a 5.3 ms peri- od (< 9 zeros in 8192 bits). if coder = 1 in the control a registers, the tneg pin becomes the ais output pin that is set high on detection of ais. the ais condition is exited when 3 9 zeros are de- tected in 8192 bits. cs61584a 20 ds261f1
cs61584a ds261pp5 21 ds261pp5 8.3 bipolar violation detection during host mode operation, a bipolar violation (bpv) is detected by the receiver and reported us- ing the latched-bpv bit in the status registers. if coder = 1 in the control a registers, the rneg pin becomes the bpv output strobe pin that is set high for one bit period on detection of a bpv. note that b8zs (or hdb3) zero substitutions are not flagged as bipolar violations if the b8zs (or hdb3) decoder has been enabled (coder = 1 and ami-r = 0 in the control a registers). 8.4 excessive zeros detection during host mode operation if coder = 1 and exz = 1 in the control a register, the bpv output pin is or'ed with receive excessive zero events. in ami mode when ami-rx = 1, the bpv pin is set high for one bit period when 16 or more consecu- tive zeros are received. in b8zs mode when ami- rx = 0, the bpv pin is set high for one bit period when 8 or more consecutive zeros are received. this is in accordance with the ansi t1.231 speci- fication. for e1 operation with hdb3 disabled, the excessive zeros detection is also disabled. for e1 with hdb3 enabled the bpv pin goes high for ev- ery set of 4 consecutively received zeros. 8.5 loss of signal during hardware mode and host mode operation, the loss of signal (los) condition is detected by the receiver and reported when the los pin is set high. loss of signal is indicated when 175 15 consecu- tive zeros are received, or when the receive (rtip/rring) signal level drops below the receiv- er sensitivity of the device. the los condition is exited according to the ansi t1.231-1993 criteria that requires a minimum 12.5% ones density signal over 175 75 bit periods with no more than 100 consecutive zeros. during los, recovered data is squelched and zeroes are output on rpos/rneg (rdata). during host mode operation, los is reported us- ing the los and latched-los bits in the status registers. note that both the los pin and register indications are available in host mode operation. the los pin and/or bit is set high when the device is reset, in power-up, or a channel is powered-down and returns low when data is recovered by the re- ceiver. during los condition the rpos (rdata), rneg pins are forced low, except when lloop1 (digital loopback) is enabled, or when the aao (automatic all ones) bit is set in the channel 1 mask register. setting the aao bit high forces un- framed all ones pattern out on the rpos (rda- ta), rneg pins when los condition occurs. when the jitter attenuator is in the receive path and los occurs, the frequency of the last valid recov- ered signal is held at rclk. when the jitter atten- uator is not in the receive path, the output frequency becomes the frequency of the reference clock. 8.6 transmit all ones during hardware mode operation, transmit all ones (taos) is selected by setting the taos pin high. during host mode, taos is controlled using the taos bit in the control b registers. selecting taos causes continuous ones to be transmitted to the line on ttip and tring at the frequency of refclk. in this mode, the transmit data inputs tpos and tneg (or tdata) are ig- nored. a taos request overrides the data transmit- ted to the line interface during local and remote loopbacks. note that the clklost interrupt is not available for tclk in the taos mode. 8.7 receive all ones during host mode operation, the data at rpos and rneg (or rdata) may be forced to output an un- framed all-ones pattern by setting both the lloop1 and lloop2 bits in the control b regis- ter to "1". an automatic receive all ones (aao) cs61584a ds261f1 21
cs61584a 22 ds261pp5 ds261pp5 response to a loss of signal condition for either channel is activated by setting bit 1 of the channel 1 mask register to 1. 8.8 local loopback selecting lloop causes the tclk, tpos, and tneg (or tdata) inputs to be looped back through the jitter attenuator (if enabled) to the rclk, rpos, and rneg (or rdata) outputs. the receive line interface is ignored, but data at tpos and tneg (or tdata) continues to be transmitted to the line interface at ttip and tring. during hardware mode operation, simul- taneous local loopback 2 of both channels is select- ed by setting the lloop pin high. during host mode operation, local loopback 1 on a per channel basis is controlled using the lloop1 bit in the control b registers. during hardware mode operation, a per channel lo- cal loopback 1 is performed when both the rloop and taos pins are high. the data at tpos and tneg is overridden with an all-ones pattern (taos) and the receive input at rtip and rring is ignored. during host mode operation, local loopback 2 can also be selected using the lloop2 bit in the control b registers. selecting lloop2 causes the tclk, tpos, and tneg (or tdata) inputs to be looped back to the rclk, rpos, and rneg (or rdata) outputs. the line driver, line receiver, and jitter at- tenuator (if enabled) are also included. the receive line interface is ignored, but data at tpos and tneg (or tdata) continues to be transmitted to the line interface at ttip and tring. a taos request overrides the data transmitted to the line interface during both local loopbacks. a taos request also overrides the data received at rpos and rneg (or rdata) during local loop- back 2. note that simultaneous selection of local and remote loopback modes is not valid. 8.9 remote loopback during hardware mode operation, remote loop- backs of either channel is selected by setting the rloop pin high. during host mode operation, re- mote loopback of each channel is controlled using the rloop bit in the control b registers. selecting rloop causes the data received from the line interface at rtip and rring to be looped back through the jitter attenuator (if enabled) and retransmitted on ttip and tring. data input to tpos and tneg (or tdata) is ignored, but data recovered from rtip and rring continues to be output on rpos and rneg (or rdata). remote loopback is functional if tclk is absent. a taos request overrides the data transmitted to the line interface during a remote loopback. note that simultaneous selection of local and remote loopback modes is not valid. 8.10 driver tristate the drivers may be independently tristated in all modes of operation. during hardware mode opera- tion, setting the con[3:0] pins of a channel to "111x" will tristate the driver. during host mode se- rial port operation, the ztx1 and ztx2 pins perform the driver tristate function and setting the con[3:0] bits in the control b registers to "111x" will also tristate the driver. during host mode parallel port op- eration, setting the con[3:0] bits in the control b register to "111x" tristates the driver. in host mode, the cs61584a powers up with con[3:0] set to 1110, which tristates the transmitter. 8.11 power down during hardware mode operation, channel power down is selected by setting the pd1 or pd2 pin high. during host mode operation, channel power down is controlled using the pd bit in the control a registers. power down places the transmitter, re- ceiver, and jitter attenuator in reset. the rclk, rpos, rneg, rdata, ais, bpv, ttip, and tring output pins are placed in a high-impedance cs61584a 22 ds261f1
cs61584a ds261pp5 23 ds261pp5 state. los will go high, and the status register will be reset, but the control, mask, and arbitrary waveform registers remain unchanged. the chan- nel not in power down and the processor port will still to operate normally. simultaneously selecting pd1 and pd2 will place all the above-mentioned pins in high impedance state and power down additional analog circuitry that is shared by both channels. the status registers are reset. in the hardware mode all output pins are tri-stated and internally pulled up to the positive supply rail. after exiting the power down state, the channel will be fully operational in less than 20 ms. 8.12 reset pin the cs61584a is continuously calibrated during operation to insure the performance of the device over power supply and temperature. this continu- ous calibration function eliminates the need to reset the line interface during operation. during hardware and host modes of operation, a device reset is selected by setting the reset pin high for a minimum of 200 ns. the reset function initiates on the falling edge of reset and requires less than 20 ms to complete. the control logic and register set are initialized and the transmit and re- ceive circuitry is calibrated if refclk and tclk are present. during host mode operation, a reset event is indicated by the latched-reset bit in the status register. 9. host mode host mode allows the cs61584a to be configured and monitored using an internal register set. this option is selected when the mode pin is set high. using the p/s pin, serial or 8-bit parallel interface ports are available in host mode. during serial port operation, the registers are specified by a 6-bit ad- dress in the range of 0x10 to 0x19. during parallel port operation, the registers are specified by an 8- bit address. the four most significant bits of the ad- dress selects one of 16 devices on the board, estab- lished by the sad[7:4] pins. the four least significant bits of the address specify the register address in the range of 0x00 to 0x09 for the selected device. parallel port option is compatible with mo- torola and intel 8-bit, multiplexed address/data bus. 9.1 register set the register set available during host mode opera- tion is presented in table 4. 9.1.1 status registers the status registers are read-only registers and are shown in table 5. the cs61584a generates an in- terrupt on the int pin any time an unmasked status register bit changes. when bts is low (intel mode), the ipol pin determines the polarity of the int pin. when bts is high (motorola mode), int polarity is active low (ipol becomes dtack ). reading both status register clears the interrupt and deactivates the int pin. los: set high while the loss of signal condition is detected. reading the status register does not clear the los bit. a los interrupt is generated only on the falling edge of the los alarm condition. the latched-los bit generates an interrupt on the ris- ing edge of los. refer to the timing diagram in figure 18. serial port address parallel port address* description 0x10 0xy0 ch 1 status 0x11 0xy1 ch 2 status 0x12 0xy2 ch 1 mask 0x13 0xy3 ch 2 mask 0x14 0xy4 ch 1 control a 0x15 0xy5 ch 2 control a 0x16 0xy6 ch 1 control b 0x17 0xy7 ch 2 control b 0x18 0xy8 ch 1 arbitrary pulse shape 0x19 0xy9 ch 2 arbitrary pulse shape *y denotes the sad[7:4] address of the cs61584a device. table 4. cs61584a register set cs61584a ds261f1 23
cs61584a 24 ds261pp5 ds261pp5 latched-los: set high on the rising edge of the loss of signal condition. reading the status register clears the latched-los bit and deactivates the int pin. refer to the timing diagram in figure 18. ais: set high while the alarm indication signal is detected. reading the status register does not clear the ais bit. an ais interrupt is generated only on the falling edge of the ais alarm condition. the latched-ais bit generates an interrupt on the rising edge of ais. refer to the timing diagram in figure 18. status register (channel 1) serial port address: 0x10; parallel port address: 0xy0 bit description definition reset value 10 7 los1 los currently detected no los 1 6 latched-los1 los event since last read no los 1 5 ais1 ais currently detected no ais 0 4 latched-ais1 ais event since last read no ais 0 3 latched-bpv1 bpv event since last read no bpv 0 2 latched-overflow1 pulse overflow since last read no overflow 0 1 latched-reset reset event since last read no reset 1 0 interrupt1 interrupt event since last read no interrupt 1 status register (channel 2) serial port address: 0x11; parallel port address: 0xy1 bit description definition reset value 10 7 los2 los currently detected no los 1 6 latched-los2 los event since last read no los 1 5 ais2 ais currently detected no ais 0 4 latched-ais2 ais event since last read no ais 0 3 latched-bpv2 bpv event since last read no bpv 0 2 latched-overflow2 pulse overflow since last read no overflow 0 1 latched-clklost tclk or refclk absent tclk and refclk present 0 0 interrupt2 interrupt event since last read no interrupt 1 table 5. status registers ais/los currently active (ais/los bit & ais/los pin) latched los (latch ais/los bit) read ais/los bits "short" ais/los event "long" ais/los event set by start of ais/los cleared by read set by change of ais/los cleared by read interrupt (int) figure 18. alarm indication event relationships cs61584a 24 ds261f1
cs61584a ds261pp5 25 ds261pp5 latched-ais: set high on the rising edge of the alarm indication signal condition. reading the sta- tus register clears the latched-ais bit and deacti- vates the int pin. refer to the timing diagram in figure 18. latched-bpv: indicates a bipolar violation has been received since the last read of the status reg- ister. reading the status register clears the latched-bpv bit and deactivates the int pin. this bit is set only when the line code decoder is enabled in the control a register. latched-overflow: indicates a waveform generat- ed using the arbitrary waveform register has ex- ceeded full scale since the last read of the status register. reading the status register clears the latched-overflow bit and deactivates the int pin. latched-reset: indicates a reset event (power-up or reset pin) has occurred since the last read of the status register. reading the status register clears the latched-reset bit and deactivates the int pin. this bit is not maskable. latched-clklost: set high when tclk or ref- clk are absent. reading the status register clears the latched-clklost bit and deactivates the int pin. interrupt: indicates a change in the status register since the last read. reading the status register clears the interrupt bit and deactivates the int pin. 9.1.2 mask registers the mask registers are read-write registers and are shown in table 6. the mask registers disables the interrupts in the corresponding status register on a per-bit basis. masking a status register bit forces it to remain at zero and prevents the int pin from ac- tivating on the condition. mask register (channel 1) serial port address: 0x12; parallel port address: 0xy2 bit description definition reset value 10 7 mask los1 mask interrupt enable interrupt 0 6 mask latched-los1 mask interrupt enable interrupt 0 5 mask ais1 mask interrupt enable interrupt 0 4 mask latched-ais1 mask interrupt enable interrupt 0 3 mask latched-bpv1 mask interrupt enable interrupt 0 2 mask latched-overflow1 mask interrupt enable interrupt 0 1 automatic all ones, aao ones at rpos/neg on los zeros at rpos/neg on los 0 0 mask interrupt1 mask interrupt enable interrupt 0 mask register (channel 2) serial port address: 0x13; parallel port address: 0xy3 bit description definition reset value 10 7 mask los2 mask interrupt enable interrupt 0 6 mask latched-los2 mask interrupt enable interrupt 0 5 mask ais2 mask interrupt enable interrupt 0 4 mask latched-ais2 mask interrupt enable interrupt 0 3 mask latched-bpv2 mask interrupt enable interrupt 0 2 mask latched-overflow2 mask interrupt enable interrupt 0 1 mask latched-clklost mask interrupt enable interrupt 0 0 mask interrupt2 mask interrupt enable interrupt 0 table 6. mask registers cs61584a ds261f1 25
cs61584a 26 ds261pp5 ds261pp5 aao: the automatic all-ones (aao) bit in the mask register (channel 1, bit 1) causes an un- framed all-ones pattern to be output at the rpos and rneg (or rdata) pins when the receiver is in a loss of signal (los) condition. 9.1.3 control a registers the control a registers are read-write registers and are shown in table 7. the control a registers se- lect device configuration and power down control. clke: establishes the edge of the of rclk that rpos and rneg (or rdata) are valid. pd: controls per channel power down. atten0 and atten1: controls the jitter attenu- ator location and -3 db knee frequency (see jitter attenuator section). coder: controls the coder mode function. the tpos, tneg, rpos, and rneg pins are active when the transparent mode is enabled. the tda- ta, rdata, ais, and bpv pins are active when the coder mode is enabled. ami-t: controls the line encoder in the transmit direction. the selection of b8zs or hdb3 is deter- mined by the con[3:0] bits (see the transmitter section). ami-r: controls the line decoder in the receive di- rection. the selection of b8zs or hdb3 is deter- mined by the con[3:0] bits (see the transmitter section). exz: controls the automatic detection of excessive zeros on the bpv pin according to ansi t1.231 when coder mode is enabled (coderx = 1). control a register (channel 1) serial port address: 0x14; parallel port address: 0xy4 bit description definition reset value 10 7 clke rpos/rneg (or rdata) valid on falling edge of rclk rpos/rneg (or rdata) valid on rising edge of rclk 0 6 pd1 power down channel power up channel 0 5 atten01 jitter attenuator location (see jitter attenuator section) 0 4atten11 0 3 coder1 coder mode enabled transparent mode enabled 0 2 ami-t1 ami encoder enabled b8zs/hdb3 encoder enabled 0 1 ami-r1 ami decoder enabled b8zs/hdb3 decoder enabled 0 0 factory test test normal operation 0 control a register (channel 2) serial port address: 0x15; parallel port address: 0xy5 bit description definition reset value 10 7 exz excessive zeros detection for both channels enabled excessive zeros detection for both channels disabled 0 6 pd2 power down channel power up channel 0 5 atten02 jitter attenuator location (see jitter attenuator section) 0 4atten12 0 3 coder2 coder mode enabled transparent mode enabled 0 2 ami-t2 ami encoder enabled b8zs/hdb3 encoder enabled 0 1 ami-r2 ami decoder enabled b8zs/hdb3 decoder enabled 0 0 factory test test normal operation 0 table 7. control a registers cs61584a 26 ds261f1
cs61584a ds261pp5 27 ds261pp5 factory test: must be cleared for normal device operation. 9.1.4 control b registers the control b registers are read-write registers and are shown in table 8. the control b registers select device configuration and loopback control. taos: controls the transmission of all ones to the line interface. a taos request overrides the data transmitted to the line interface during local and re- mote loopbacks. rloop: controls the remote loopback function for the channel. lloop1: controls the local loopback #1 function for the channel. includes the jitter attenuator, if en- abled. in host mode, selecting lloop1 and lloop2 simultaneously causes all ones to be out- put from rpos/rneg (rdata). lloop2: controls the local loopback #2 function for the channel. includes the line driver, line receiv- er, and jitter attenuator, if enabled. see lloop1, above, for receive all ones function. con[3:0]: controls the configuration of the line driver, line receiver, coder, and driver tristate as shown in the transmitter section. both channels must be configured to operate at the same rate (both t1 or both e1). 9.1.5 arbitrary waveform registers in addition to the predefined t1 and e1 pulse shapes, arbitrary pulse shapes may be created dur- ing host mode operation using the registers shown in table 9. this flexibility can be used to compen- control b register (channel 1) serial port address: 0x16; parallel port address: 0xy6 bit description definition reset value 10 7 taos1 enable transmit all ones disable transmit all ones 0 6 rloop1 enable remote loopback disable remote loopback 0 5 lloop11 enable local loopback #1 disable local loopback #1 0 4 lloop21 enable local loopback #2 disable local loopback #2 0 3 con31 line configuration selections (see transmitter section) 1 2con21 1 1con11 1 0con01 0 control b register (channel 2) serial port address: 0x17; parallel port address: 0xy7 bit description definition reset value 10 7 taos2 enable transmit all ones disable transmit all ones 0 6 rloop2 enable remote loopback disable remote loopback 0 5 lloop12 enable local loopback #1 disable local loopback #1 0 4 lloop22 enable local loopback #2 disable local loopback #2 0 3 con32 line configuration selections (see transmitter section) 1 2con22 1 1con12 1 0con02 0 table 8. control b registers cs61584a ds261f1 27
cs61584a 28 ds261pp5 ds261pp5 sate for waveform degradation that may result from non-standard cables, transformers, or protection circuitry. arbitrary waveform generation is enabled when the con[3:0] line configuration selection in the con- trol b register is set to one of four arbitrary wave- form modes (see the transmitter section). the arbitrary pulse shape of mark (a transmitted "1") is specified by describing the pulse shape across three unit intervals (uis). one ui in ds1 applications is 648 ns (1.544 mhz period) and one ui in e1 appli- cations is 488 ns (2.048 mhz period). for example, arbitrary waveform generation allows the dsx-1 return-to-zero "tail" to extend further into the next ui or allows t1 long-haul waveforms to be defined across all three uis. the amplitude of a space (a transmitted "0") is fixed at zero volts. all three uis are divided into 14 equal phases for a total of 42 phase segments. the shape of the pulse is then defined by writing the amplitude of each phase segment to the arbitrary waveform register 42 times in sequence from ui1/phase1 to ui3/phase14. the custom pulse shape must be de- fined using the arbitrary waveform register before setting the con[3:0] configuration selection to one of the arbitrary generation settings (i.e., 1001, 1010, or 1011). for ds1 applications, the cs61584a divides the 648 ns ui into 14 equal phases of 46.3 ns. for dsx-1 applications, the 648 ns ui is divided into 13 equal phases of 49.8 ns. the phase amplitude in- formation written for phase 14 of each ui is ig- nored. for e1 applications, the 488 ns ui is divided into 12 equal phases of 40.7 ns. the phase ampli- arbitrary waveform register (channel 1) serial port address: 0x18; parallel port address: 0xy8 bit description definition reset value 10 70 arbitrary pulse shape definitions undefined 6msb 5 4 3 2 1 0lsb arbitrary waveform register (channel 2) serial port address: 0x19; parallel port address: 0xy9 bit description definition reset value 10 7 0 arbitrary pulse shape definitions undefined 6msb 5 4 3 2 1 0lsb table 9. arbitrary waveform registers cs61584a 28 ds261f1
cs61584a ds261pp5 29 ds261pp5 tude information written for phases 13 and 14 of each ui is ignored. examples of arbitrary wave- forms are illustrated in figure 19. the amplitude of each phase segment is described by a 7-bit, 2's complement number (bit 8 is ig- nored). a positive value describes pulse amplitude and a negative value describes pulse undershoot. for dsx-1 applications with con[3:0] = 1010, the typical output voltage step is 73 mv/lsb across the secondary (line side) of the transformer. for ds1 applications with con[3:0] = 1011, the typi- cal output voltage step is 52 mv/lsb across the transformer secondary. for e1 75 w coaxial appli- cations with con[3:0] = 1000, the typical output voltage step is 43 mv/lsb. for e1 120 w twisted- pair applications with con[3:0] = 1001, the typi- cal output voltage step is 52 mv/lsb. the full scale positive value is 0x3f and the full scale negative value is 0x40. it is recommended that the output voltage across the secondary of the transformer (line interface side) be limited to 4.4 vpk. at higher output voltages, the transmitter may not be able to drive the requested voltage based on the current operating conditions. because the transmitter drives either a mark or a space to the line interface every ui, the phase am- plitude information defined in ui2 and ui3 is add- ed to the symbols transmitted at ttip and tring in those intervals. therefore, a mark defined only for ui1 will be output exactly as programmed if an- other mark is transmitted in the next two ui. how- ever, a mark defined over ui1 and ui2 with an extended return-to-zero "tail" will cause the lead- ing edge of a mark transmitted in the next ui to rise or fall more quickly. this is illustrated in figure 20. if the hexadecimal sum of the phase amplitudes ex- ceeds the full scale values, the sum is replaced by the full scale value and the latched-overflow bit is set in the status register. e1 arbitrary waveform example dsx-1 (54% duty cycle) arbitrary waveform example ds-1 (50% duty cycle) arbitrary waveform example figure 19. phase definition of arbitrary waveforms figure 20. example of summing of waveforms cs61584a ds261f1 29
cs61584a 30 ds261pp5 ds261pp5 9.2 serial port operation serial port operation in host mode is selected when the mode pin is set high and the p/s pin is set low. in this mode, the cs61584a register set is accessed by setting the chip select (cs ) pin low and commu- nicating over the sdi, sdo, and sclk pins. tim- ing over the serial port is independent of the transmit and receive system timing. figure 21 illus- trates the format of serial port data transfers. a read or write is initiated by writing an ad- dress/command byte (acb) to sdi. during a read cycle, the register data addressed by the acb is output on sdo on the next eight sclk clock cy- cles. during a write cycle, the data byte immediate- ly follows the acb. a second address byte is required when reading or writing the arbitrary waveform registers (see below). data is written to and read from the serial port in lsb first format. when writing to the port, sdi in- put data is sampled by the device on the rising edge of sclk. the polarity of the data output on sdo is controlled by the spol pin. when the spol pin is low, data on sdo is valid on the rising edge of sclk. when the spol pin is high, data on sdo is valid on the falling edge of sclk. the sdo pin is high impedance when not transmitting data. if the host processor has a bi-directional i/o port, sdi and sdo may be tied together. as illustrated in figure 22, the acb consists of a r/w bit, address field, and two reserved bits. the r/w bit specifies if the current register access is a read (r/w = 1) or a write (r/w = 0) operation. the address field specifies the register address from 0x10 to 0x19. the reserved bit must be cleared for normal operation of serial mode. during register addressing, the first eight registers are addressed as 0x10 to 0x17 in the address field of the acb. because arbitrary waveform registers 0x18 and 0x19 access multiple bytes of ram, reading or writing these registers requires an ad- dress command byte followed by a ram address byte for each data transfer. the acb specifies ei- ther 0x18 or 0x19 in the address field to access the channel 1 or channel 2 arbitrary waveform regis- ter set. the ram address is an 8-bit, unsigned bi- nary number in the range of 0x00 to 0x29 to identify one of 42 ram locations. the data byte containing the 7-bit, 2's complement number spec- ifying the phase amplitude completes the 24 sclk write cycle. cs sclk sdo sdi d6 d5 d4 d3 d2 d1 d0 d7 0 0 d7 d6 d5 d4 d3 d2 d1 d0 address/command byte(s) data output 0 0 0 1 0 r/w data input figure 21. serial read/write format (spol = 0) figure 22. address command byte b7 (msb)b6b5b4b3b2b1b0 reserved reserved adr4 adr3 adr2 adr1 adr0 r/w 0 0 msb address field lsb 0 = write 1 = read cs61584a 30 ds261f1
cs61584a ds261pp5 31 ds261pp5 9.3 parallel port operation parallel port operation in host mode is selected when the mode and p/s pins are set high. in this mode, the cs61584a register set is accessed using an 8-bit, multiplexed bi-directional address/data bus ad[7:0]. timing over the serial port is inde- pendent of the transmit and receive system timing. the device is compatible with both intel and mo- torola bus formats. the intel bus format is selected when the bts pin is low and the motorola bus for- mat is selected when the bts pin is high. a read or write is initiated by writing an address byte to ad[7:0]. the device latches the address on the fall- ing edge of ale(as). during a read cycle, the reg- ister data is output during the later portion of the rd or ds pulses. the read cycle is terminated and the bus returns to a high impedance state as rd transitions high in intel timing or ds transitions low in motorola timing. during a write cycle, valid write data must be present and held stable during the later portion of the wr or ds pulses. a second address byte is required when reading or writing the arbitrary waveform registers (see below). a read or write over the parallel port is initiated by writing an address byte to ad[7:0]. the address byte consists of two nibbles. the four most signifi- cant bits ad[7:4] select one of 16 cs61584a de- vices in the application. this device address value is established by the sad[7:4] pins. the four least significant bits ad[3:0] are the register address for the selected device, ranging from 0x00 to 0x09. the first eight device registers are addressed from 0x00 to 0x07 in the four least significant bits of the address. because arbitrary waveform registers 0x08 and 0x09 access multiple bytes of ram, reading or writing these registers requires an addi- tional ram address byte for each data transfer. the ram address is an 8-bit, unsigned binary number in the range of 0x00 to 0x29 to identify one of 42 ram locations. the data byte containing the 7-bit, 2's complement number specifying the phase amplitude completes a write cycle. the sequence for writing to ram is: first ale(as) addresses the device, a second ale(as) addresses the ram, then a rd or wr (r/w ) accesses the ram data. 10. jtag boundary scan board testing is supported through jtag boundary scan. using boundary scan, the integrity of the dig- ital paths between devices on a circuit board can be verified. this verification is supported by the abil- ity to externally set the signals on the digital output pins of the cs61584a, and to externally read the signals present on the input pins of the cs61584a. additionally, the manufacturer id, part number and revision of the device can be read during board test using jtag boundary scan. as shown in figure 23, the jtag hardware con- sists of data and instruction registers plus a test access port (tap) controller. control of the tap is achieved through signals applied to the test mode select (j-tms) and test clock (j-tck) in- put pins. data is shifted into the registers via the test data input (j-tdi) pin, and shifted out of the registers via the test data output (j-tdo) pin. both j-tdi and j-tdo are clocked at a rate deter- mined by j-tck. the instruction register defines which data register is accessed in the shift opera- tion. note that if j-tdi is floating, an internal pull- up resistor forces the pin high. mux j-tdi j-tck j-tms j-tdo jtag block boundary scan data register digital output pins digital input pins parallel latched output tap controller instruction (shift) register bypass data register device id data register parallel latched output figure 23. jtag circuitry block diagram cs61584a ds261f1 31
cs61584a 32 ds261pp5 ds261pp5 10.1 jtag data registers (dr) the test data registers are the boundary-scan reg- ister (bsr), the device identification register (dir), and the bypass register (br). boundary scan register: the bsr is connected in parallel to all the digital i/o pins, and provides the mechanism for applying/reading test patterns to/from the board traces. the bsr is 62 bits long and is initialized and read using the instruction sample/preload. the bit ordering for the bsr is the same as the top-view package pin out, beginning with the los1 pin and moving counter- clockwise to end with the pd1 pin as shown in ta- ble 10. note that the analog, oscillator, power, ground, clke/ipol, and mode pins are not in- cluded as part of the boundary-scan register. the input pins require one bit in the bsr and only one j-tck cycle is required to load test data for each input pin. the output pins have two bits in the bsr to define output high, output low, or high impedance. the first bit (shifted in first) selects between an output- enabled state (bit set to 1) or high-impedance state (bit set to 0). the second bit shifted in contains the test data that may be output on the pin. therefore, two j-tck cycles are required to load test data for each output pin. the bi-directional pins have three bits in the bsr to define input, output high, output low, or high im- pedance. the first bit shifted into the bsr config- ures the output driver as high-impedance (bit set to 0) or active (bit set to 1). the second bit shifted into the bsr sets the output value when the first bit is 1. the third bit captures the value of the pin. this pin may have its value set externally as an input (if the first bit is 0) or set internally as an output (if the first bit is 1). to configure a pad as an input, the j- tdi pattern is 0x0. to configure a pad as an out- put, the j-tdi pattern is 1x1. therefore, three j- tck cycles are required to load test data for each bi-directional pin. when jtag testing is conducted in host mode, the polarity of the int pin is determined by the state of the ipol pin. the jtag bsr should configure the int pin as an input in hardware mode and as an output in host mode. device identification register: the dir provides the manufacturer, part number, and version of the cs61584a. this information can be used to verify that the proper version or revision number has been used in the system under test. the dir is 32 bits long and is partitioned as shown in table 11. data from the dir is shifted out to j-tdo lsb first. bsr bits pin name pad type 0 - 2 los1, sad6 bi-directional 3 - 5 tneg1, ais1 bi-directional 6 tpos1, tdata1 input 7tclk1input 8 - 9 rneg1, bpv1 output 10 - 11 rpos1, rdata1 output 12 - 13 rclk1 output 14 atten1, cs input 15 - 17 rloop1, int bi-directional 18 rloop2, sclk, rd (ds) input 19 - 21 lloop, sdo, ad0 bi-directional 22 - 24 taos1, sdi, ad1 bi-directional 25 - 27 taos2, spol, ad2 bi-directional 28 - 30 con01, ad3 bi-directional 31 - 33 con02, ad4 bi-directional 34 - 36 con11, ad5 bi-directional 37 - 39 con12, ad6 bi-directional 40 - 42 con21, ad7 bi-directional 43 con22, ale(as) input 44 con31, wr (r/w ) input 45 - 46 rclk2 output 47 - 48 rpos2, rdata2 output 49 - 50 rneg2, bpv2 output 51 tclk2 input 52 tpos2, tdata2 input 53 - 55 tneg2, ais2 bi-directional 56 - 58 los2, sad7 bi-directional 59 con32, bts input 60 pd2, sad5 input 61 pd1, sad4 input table 10. boundary scan register cs61584a 32 ds261f1
cs61584a ds261pp5 33 ds261pp5 bypass register: the bypass register consists of a single bit, and provides a serial path between j-tdi and j-tdo, bypassing the bsr. this allows by- passing specific devices during certain board-level tests. this also reduces test access times by reduc- ing the total number of shifts required from j-tdi to j-tdo. 10.2 jtag instructions and instruction register (ir) the instruction register (2 bits) allows the instruc- tion to be shifted into the jtag circuit. the in- struction selects the test to be performed or the data register to be accessed or both. the valid instruc- tions are shifted in lsb first and are listed in table 12: extest instruction: the extest instruction al- lows testing of off-chip circuitry and board-level interconnect. extest connects the bsr to the j- tdi and j-tdo pins. the normal path between the cs61584a logic and i/o pins is broken. the sig- nals on the output pins are loaded from the bsr and the signals on the input pins are loaded into the bsr. sample/preload instruction: the sam- ple/preload instructions allows scanning of the boundary-scan register without interfering with the operation of the cs61584a. this instruction connects the bsr to the j-tdi and j-tdo pins. the normal path between the cs61584a logic and its i/o pins is maintained. the signals on the i/o pins are loaded into the bsr. additionally, this in- struction can be used to latch values into the digital output pins. idcode instruction: the idcode instruction connects the device identification register to the j- tdo pin. the idcode instruction is forced into the instruction register during the test-logic-reset controller state.the default instruction is idcode after a device reset. bypass instruction: the bypass instruction connects the minimum length bypass register be- tween the j-tdi and j-tdo pins and allows data to be shifted in the shift-dr controller state. 10.3 jtag tap controller figure 24 shows the state diagram for the tap state machine. a description of each state follows. note that the figure contains two main branches to ac- cess either the data or instruction registers. the val- ue shown next to each state transition in this figure is the value present at j-tms at each rising edge of j-tck. 10.4 test-logic-reset state in this state, the test logic is disabled to continue normal operation of the device. during initializa- tion, the cs61584a initializes the instruction reg- ister with the idcode instruction. regardless of the original state of the controller, the controller enters the test-logic-reset state when the j-tms input is held high for at least five rising edges of j-tck. the controller remains in this state while j-tms is high. the cs61584a pro- cessor automatically enters this state at power-up. ir code instruction 00 extest 01 sample/preload 10 idcode 11 bypass table 12. msb lsb 31 28 27 12 11 1 0 00000110011011100001000011001001 4 bits 16 bits 11 bits bit #(s) function total bits 31-28 version number 4 27-14 part number 14 13-12 derivative code 2 11-1 manufacturer number 11 0 constant logic 1 1 table 11. device identification register cs61584a ds261f1 33
cs61584a 34 ds261pp5 ds261pp5 10.5 run-test/idle state this is a controller state between scan operations. once in this state, the controller remains in the state as long as j-tms is held low. the instruction reg- ister and all test data registers retain their previous state. when j-tms is high and a rising edge is ap- plied to j-tck, the controller moves to the select- dr state. 10.6 select-dr-scan state this is a temporary controller state and the instruc- tion does not change in this state. the test data reg- ister selected by the current instruction retains its previous state. if j-tms is held low and a rising edge is applied to j-tck when in this state, the controller moves into the capture-dr state and a scan sequence for the selected test data register is initiated. if j-tms is held high and a rising edge applied to j-tck, the controller moves to the se- lect-ir-scan state. 10.7 capture-dr state in this state, the boundary scan register captures input pin data if the current instruction is extest or sample/preload. the instruction does not change in this state. the other test data registers, which do not have parallel input, are not changed. when the tap controller is in this state and a rising edge is applied to j-tck, the controller enters the exit1-dr state if j-tms is high or the shift-dr state if j-tms is low. 10.8 shift-dr state in this controller state, the test data register con- nected between j-tdi and j-tdo as a result of the current instruction shifts data on stage toward its serial output on each rising edge of j-tck. the in- struction does not change in this state. when the tap controller is in this state and a rising edge is applied to j-tck, the controller enters the exit1- dr state if j-tms is high or remains in the shift- dr state if j-tms is low. 10.9 exit1-dr state this is a temporary state. while in this state, if j- tms is held high, a rising edge applied to j-tck causes the controller to enter the update-dr state, which terminates the scanning process. if j-tms is held low and a rising edge is applied to j-tck, the controller enters the pause-dr state. the test data register selected by the current instruction retains its previous value and the instruction does not change during this state. test-logic-reset run-test/idle select-dr-scan capture-dr shift-dr exit1-dr pause-dr exit2-dr update-dr select-ir-scan capture-ir shift-ir exit1-ir pause-ir exit2-ir update-ir 1 0 0 1 1 0 1 0 1 1 0 1 0 0 1 0 1 0 0 1 1 0 1 1 0 1 0 0 1 0 1 0 figure 24. tap controller state diagram cs61584a 34 ds261f1
cs61584a ds261pp5 35 ds261pp5 10.10 pause-dr state the pause state allows the test controller to tempo- rarily halt the shifting of data through the test data register in the serial path between j-tdi and j- tdo. for example, this state could be used to al- low the tester to reload its pin memory from disk during application of a long test sequence. the test data register selected by the current instruction re- tains its previous value and the instruction does not change during this state. the controller remains in this state as long as j-tms is low. when j-tms goes high and a rising edge is applied to j-tck, the controller moves to the exit2-dr state. 10.11 exit2-dr state this is a temporary state. while in this state, if j- tms is held high, a rising edge applied to j-tck causes the controller to enter the update-dr state, which terminates the scanning process. if j-tms is held low and a rising edge is applied to j-tck, the controller enters the shift-dr state. the test data register selected by the current instruction retains its previous value and the instruction does not change during this state. 10.12 update-dr state the boundary scan register is provided with a latched parallel output to prevent changes while data is shifted in response to the extest and sample/preload instructions. when the tap controller is in this state and the boundary scan register is selected, data is latched into the parallel output of this register from the shift-register path on the falling edge of j-tck. the data held at the latched parallel output changes only in this state. all shift-register stages in the test data register se- lected by the current instruction retain their previ- ous value and the instruction does not change during this state. 10.13 select-ir-scan state this is a temporary controller state. the test data register selected by the current instruction retains its previous state. if j-tms is held low and a rising edge is applied to j-tck when in this state, the controller moves into the capture-ir state, and a scan sequence for the instruction register is initiat- ed. if j-tms is held high and a rising edge is ap- plied to j-tck, the controller moves to the test- logic-reset state. the instruction does not change during this state. 10.14 capture-ir state in this controller state, the shift register contained in the instruction register loads a fixed value of "01" on the rising edge of j-tck. this supports fault-isolation of the board-level serial test data path. data registers selected by the current instruc- tion retain their value and the instruction does not change during this state. when the controller is in this state and a rising edge is applied to j-tck, the controller enters the exit1-ir state if j-tms is held high, or the shift-ir state if j-tms is held low. 10.15 shift-ir state in this state, the shift register contained in the in- struction register is connected between j-tdi and j-tdo and shifts data one stage towards its serial output on each rising edge of j-tck. the test data register selected by the current instruction retains its previous value and the instruction does not change during this state. when the controller is in this state and a rising edge is applied to j-tck, the controller enters the exit1-ir state if j-tms is held high, or remains in the shift-ir state if j-tms is held low. cs61584a ds261f1 35
cs61584a 36 ds261pp5 ds261pp5 10.16 exit1-ir state this is a temporary state. while in this state, if j- tms is held high, a rising edge applied to j-tck causes the controller to enter the update-ir state, which terminates the scanning process. if j-tms is held low and a rising edge is applied to j-tck, the controller enters the pause-ir state. the test data register selected by the current instruction retains its previous value and the instruction does not change during this state. 10.17 pause-ir state the pause state allows the test controller to tempo- rarily halt the shifting of data through the instruc- tion register. the test data register selected by the current instruction retains its previous value and the instruction does not change during this state. the controller remains in this state as long as j- tms is low. when j-tms goes high and a rising edge is applied to j-tck, the controller moves to the exit2-ir state. 10.18 exit2-ir state this is a temporary state. while in this state, if j- tms is held high, a rising edge applied to j-tck causes the controller to enter the update-ir state, which terminates the scanning process. if j-tms is held low and a rising edge is applied to j-tck, the controller enters the shift-ir state. the test data register selected by the current in- struction retains its previous value and the instruc- tion does not change during this state. 10.19 update-ir state the instruction shifted into the instruction register is latched into the parallel output from the shift-reg- ister path on the falling edge of j-tck. when the new instruction has been latched, it becomes the current instruction. the test data registers selected by the current instruction retain their previous val- ue. 10.20 jtag application examples figures 25 and 26 illustrate examples of updating the instruction and data registers during jtag op- eration. cs61584a 36 ds261f1
cs61584a ds261pp5 37 ds261pp5 tck tms controller state tdi ir shift-register parallel output of ir parallel input to tdr tdr shift-register parallel output of tdr register selected tdo enable tdo act idcode new instruction old data instruction register inactive active inactive inactive = don't care or undefined parallel input to ir test-logic-reset run-test/idle select-dr-scan select-ir-scan capture-ir pause-ir exit2-ir shift-ir exit1-ir update-ir run-test/idle exit1-ir shift-ir figure 25. jtag instruction register update cs61584a ds261f1 37
cs61584a 38 ds261pp5 ds261pp5 tck tms controller state tdi parallel input to ir ir shift-register parallel output of ir parallel input to tdr tdr shift-register register selected tdo enable tdo = don't care or undefined parallel output of tdr test-logic-reset run-test/idle select-dr-scan select-dr-scan capture-dr pause-dr exit2-dr shift-dr update-dr run-test/idle exit1-dr shift-dr exit1-dr select-ir-scan idcode instruction old data test data register new data inactive active inactive inactive active figure 26. jtag data register update cs61584a 38 ds261f1
cs61584a ds261pp5 39 ds261pp5 11. pin descriptions power supplies agnd - analog ground (plcc pin 33; tqfp pin 23) analog supply ground pin. av+ - analog power supply (plcc pin 34; tqfp pin 24) analog supply pin for internal bandgap reference, oscillator, and timing generation circuits. bgref - bandgap reference (plcc pin 32; tqfp pin 22) this pin is used by the internal bandgap reference and must be connected to ground by a 4.99 k w 1% resistor to provide an internal current reference. dgnd1, dgnd2, dgnd3 - digital ground (plcc pins 1, 18, 67; tqfp pins 57, 9, 55) power supply ground pins for the digital circuitry of both channels. dv+ - digital power supply (plcc pin 68; tqfp pin 56) power supply pin for the digital circuitry of both channels. 41 43 45 47 33 35 37 39 7 5 3 1 15 13 11 9 17 19 21 23 25 27 29 31 63 61 59 57 55 53 51 49 8 6 4 2 16 14 12 10 18 20 22 24 26 28 30 32 42 44 46 48 34 36 38 40 64 62 60 58 56 54 52 50 cs61584a 64-pin tqfp top view dgnd1 ad3 ad2 ad1 tgnd1 tring1 sad4 p/s rtip1 rring1 rv+1 rgnd1 dgnd2 j-tdi ttip1 tv+1 tpos1(tdata1) tneg1(ais1) sad6 j-tdo rclk1 rpos1(rdata1) rneg1(bpv1) tclk1 ad0 rd(ds) int cs mode bgref agnd av+ dgnd1 not used spol sdi tgnd1 tring1 ztx1 p/s rtip1 rring1 rv+1 rgnd1 dgnd2 j-tdi ttip1 tv+1 tpos1(tdata1) tneg1(ais1) los1 j-tdo rclk1 rpos1(rdata1) rneg1(bpv1) tclk1 sdo sclk int cs mode bgref agnd av+ dgnd1 con01 taos2 taos1 tgnd1 tring1 pd1 atten0 rtip1 rring1 rv+1 rgnd1 dgnd2 j-tdi ttip1 tv+1 tpos1 tneg1 los1 j-tdo rclk1 rpos1 rneg1 tclk1 lloop rloop2 rloop1 atten1 mode bgref agnd av+ hardware mode host mode serial port host mode parallel port dv+ dgnd3 con02 con11 con12 con21 con22 con31 rclk2 rpos2 rneg2 tclk2 tpos2 tneg2 los2 con32 j-tck j-tms ttip2 tv+2 tgnd2 tring2 pd2 clke rtip2 rring2 rv+2 rgnd2 1xclk xtalout refclk reset dv+ dgnd3 not used not used not used not used not used not used rclk2 rpos2(rdata2) rneg2(bpv2) tclk2 tpos2(tdata2) tneg2(ais2) los2 not used j-tck j-tms ttip2 tv+2 tgnd2 tring2 ztx2 ipol rtip2 rring2 rv+2 rgnd2 1xclk xtalout refclk reset dv+ dgnd3 ad4 ad5 ad6 ad7 ale(as) wr(r/w) rclk2 rpos2(rdata2) rneg2(bpv2) tclk2 tpos2(tdata2) tneg2(ais2) sad7 bts j-tck j-tms ttip2 tv+2 tgnd2 tring2 sad5 ipol/dtack rtip2 rring2 rv+2 rgnd2 1xclk xtalout refclk reset hardware mode host mode serial port host mode parallel port pins labeled as not used should be tied to ground. cs61584a ds261f1 39
cs61584a 40 ds261pp5 ds261pp5 rgnd1, rgnd2 - receiver ground (plcc pins 30, 39; tqfp pins 20, 29) power supply ground pins for the receiver circuitry. rv+1, rv+2 - receiver power supply (plcc pins 29, 40; tqfp pins 19, 30) power supply pins for the analog receiver circuitry. tgnd1, tgnd2 - transmit ground (plcc pins 22, 47; tqfp pins 13, 36) power supply ground pins for the transmitter circuitry. tv+1, tv+2 - transmit power supply (plcc pins 21, 48; tqfp pins 12, 37) power supply pins for the analog transmitter circuitry. 53 55 57 59 44 46 48 50 16 14 12 10 25 23 21 19 27 29 31 33 36 38 40 42 8 6 4 2 67 65 63 61 17 15 13 11 26 24 22 20 28 30 32 34 37 39 41 43 54 56 58 60 45 47 49 51 9 7 5 3 68 66 64 62 cs61584a 68-pin plcc top view 18 52 1 35 dgnd1 ad3 ad2 ad1 ad0 rd(ds) int cs dgnd1 not used spol sdi sdo sclk int cs dgnd1 con01 taos2 taos1 lloop rloop2 rloop1 atten1 hardware mode host mode serial port host mode parallel port dv+ dgnd3 con02 con11 con12 con21 con22 con31 dv+ dgnd3 not used not used not used not used not used not used dv+ dgnd3 ad4 ad5 ad6 ad7 ale(as) wr(r/w) hardware mode host mode serial port host mode parallel port not used not used not used tgnd1 tring1 sad4 p/s dgnd2 j-tdi ttip1 tv+1 tpos1(tdata1) tneg1(ais1) sad6 j-tdo rclk1 rpos1(rdata1) rneg1(bpv1) tclk1 tgnd1 tring1 ztx1 p/s dgnd2 j-tdi ttip1 tv+1 tpos1(tdata1) tneg1(ais1) los1 j-tdo rclk1 rpos1(rdata1) rneg1(bpv1) tclk1 tgnd1 tring1 pd1 atten0 dgnd2 j-tdi ttip1 tv+1 tpos1 tneg1 los1 j-tdo rclk1 rpos1 rneg1 tclk1 not used not used not used rtip1 rring1 rv+1 rgnd1 mode bgref agnd av+ rtip1 rring1 rv+1 rgnd1 mode bgref agnd av+ rtip1 rring1 rv+1 rgnd1 mode bgref agnd av+ not used not used not used rclk2 rpos2 rneg2 tclk2 tpos2 tneg2 los2 con32 j-tck j-tms ttip2 tv+2 tgnd2 tring2 pd2 clke rclk2 rpos2(rdata2) rneg2(bpv2) tclk2 tpos2(tdata2) tneg2(ais2) los2 not used j-tck j-tms ttip2 tv+2 tgnd2 tring2 ztx2 ipol rclk2 rpos2(rdata2) rneg2(bpv2) tclk2 tpos2(tdata2) tneg2(ais2) sad7 bts j-tck j-tms ttip2 tv+2 tgnd2 tring2 sad5 ipol/dtack not used not used not used rtip2 rring2 rv+2 rgnd2 1xclk xtalout refclk reset rtip2 rring2 rv+2 rgnd2 1xclk xtalout refclk reset rtip2 rring2 rv+2 rgnd2 1xclk xtalout refclk reset pins labeled as not used should be tied to ground. cs61584a 40 ds261f1
cs61584a ds261pp5 41 ds261pp5 t1/e1 data inputs and outputs rclk1, rclk2 - receive clock (plcc pins 10, 59; tqfp pins 1, 48) rpos1, rpos2 - receive positive data (plcc pins 11, 58; tqfp pins 2, 47) rneg1, rneg2 - receive negative data (plcc pins 12, 57; tqfp pins 3, 46) the receiver recovered clock and nrz digital data from rtip and rring is output on these pins. during hardware mode operation, the clke pin determines the clock edge on which rpos and rneg are stable and valid. during host mode operation, the clke bit in the control a register determines the clock edge on which rpos and rneg are stable and valid. a positive pulse (with respect to ground) received on rtip generates a logic 1 on rpos, and a positive pulse received on rring generates a logic 1 on rneg. rdata1, rdata2 - receive data [host mode] (plcc pins 11, 58; tqfp pins 2, 47) during host mode operation with the coders enabled, the decoded digital data stream from rtip and rring is output on rdata in nrz format. the clke bit in the control a register determines the clock edge on which rdata is stable and valid. rtip1, rtip2 - receive tip (plcc pins 27, 42; tqfp pins 17, 32) rring1, rring2 - receive ring (plcc pins 28, 41; tqfp pins 18, 31) the receive ami signal from the line interface is input on these pins. the recovered clock and data are output on rclk, rpos, and rneg (or rdata). tclk1, tclk2 - transmit clock (plcc pins 13, 56; tqfp pins 4, 45) tpos1, tpos2 - transmit positive data (plcc pins 14, 55; tqfp pins 5, 44) tneg1, tneg2 - transmit negative data (plcc pins 15, 54; tqfp pins 6, 43) the transmit clock and data are input to these pins. the signal is driven to the line interface at ttip and tring. data on tpos and tneg are sampled on the falling edge of tclk. an input on tpos causes a positive pulse to be transmitted at ttip and tring, while an input on tneg causes a negative pulse to be transmitted at ttip and tring. tdata1, tdata2 - transmit data [host mode] (plcc pins 14, 55; tqfp pins 5, 44) during host mode operation with the coders enabled, the un-encoded digital data stream is input on tdata in nrz format. data at tdata is sampled on the falling edge of tclk. ttip1, ttip2 - transmit tip (plcc pins 20,49; tqfp pins 11, 38) tring1, tring2 - transmit ring (plcc pins 23, 46; tqfp pins 14, 35) the transmit ami signal to the line interface is output on these pins. the transmit clock and data are input on tclk, tpos, and tneg (or tdata). oscillator 1xclk - one-times clock frequency select (plcc pin 38; tqfp pin 28) when 1xclk is high, refclk must be a 1x clock (i.e., 1.544 mhz for t1 applications or 2.048 mhz for e1 applications). when 1xclk is low, refclk must be an 8x clock (i.e., 12.352 mhz for t1 applications or 16.384 mhz for e1 applications). cs61584a ds261f1 41
cs61584a 42 ds261pp5 ds261pp5 refclk - external reference clock input (plcc pin 36; tqfp pin 26) input reference clock for the receive and jitter attenuator circuits. when 1xclk is high, refclk must be a 1x clock (i.e., 1.544 mhz 100 ppm for t1 applications or 2.048 mhz 100 ppm for e1 applications). when 1xclk is set low, refclk must be an 8x clock (i.e., 12.352 mhz 100 ppm for t1 applications or 16.384 mhz 100 ppm for e1 applications). the refclk input also determines the transmission rate when taos is asserted. xtalout - crystal oscillator output (plcc pin 37; tqfp pin 27) a quartz crystal with a resonant frequency of 12.352 mhz for t1 applications or 16.384 mhz for e1 applications may be connected across the xtalout and refclk pins instead of using a cmos compatible clock source. the 1xclk pin must be set low to select 8x clock operation. this pin must remain unconnected if a quartz crystal is not used. control atten0, atten1 - attenuator select [hardware mode] (plcc pins 25, 8; tqfp pins 16, 64) selects the jitter attenuator path and -3 db knee point for both channels (transmit/receive/neither). see table 3. clke - clock edge [hardware mode] (plcc pin 44; tqfp pin 33) controls the polarity of the recovered clock rclk. when clke is high, rpos and rneg (or rdata) are valid on the falling edge of rclk. when clke is low, rpos and rneg (or rdata) are valid on the rising edge of rclk. con01, con11 - configuration selection for channel 1 [hardware mode] con21, con31 - (plcc pins 2, 65, 63, 61; tqfp pins 58, 53, 51, 49) con02, con12 - configuration selection for channel 2 [hardware mode] con22, con32 - (plcc pins 66, 64, 62, 52; tqfp pins 54, 52, 50, 41) these pins configure the transmitter (pulse shape, pulse width, pulse amplitude, and driver impedance), receiver (slicing level), coder (hdb3 vs b8zs), and driver tristate. the conx1 pins control channel 1 and the conx2 pins control channel 2. both channels must be configured to operate at the same data rate on the line interface (both t1 or both e1). the arbitrary waveform options are not available during hardware mode operation. see table 1. lloop - local loopback [hardware mode] (plcc pin 5; tqfp pin 61) a local loopback #2 of both channels is enabled when lloop is high. selecting lloop causes the tclk, tpos/tneg (tdata) inputs to be looped back through the transmitter, receiver and jitter attenuator (if enabled) to the rclk, rpos/rneg (rdata) outputs. the data at tpos/tneg (tdata) continues to be transmitted to the line interface unless overridden by a taos request. the input on rtip and rring is ignored. when the rloop and taos pins are both high, the tclk, tpos/tneg (tdata) inputs are looped back (local loopback #1) through the jitter attenuator (if enabled) to the rclk, rpos/rneg (rdata) outputs for the selected channel. the data at tpos/tneg (tdata) is also overridden with an all-ones pattern (taos). the receive input at rtip and rring is ignored. mode - mode select (plcc pin 31; tqfp pin 21) hardware mode operation is selected when mode is low, enabling the device to be configured and monitored using control pins. host mode operation is selected when mode is high, enabling the device to be configured and monitored over a microprocessor interface using the internal register set. cs61584a 42 ds261f1
cs61584a ds261pp5 43 ds261pp5 pd1, pd2 - power down [hardware mode] (plcc pins 24, 45; tqfp pins 15, 34) setting pd high places the channel in a low power, inactive state. power down forces the transmitter, receiver, and jitter attenuator to the reset state. all device outputs are forced to a high impedance state to facilitate circuit board testing. ztx1 - driver tristate [host mode - serial port] ztx2 - (plcc pins 24, 45; tqfp pins 15, 34) setting ztx high causes the driver at ttip and tring to be placed in a tristate (high-impedance) condition. reset - reset (plcc pin 35; tqfp pin 25) a device reset is selected by setting the reset pin high for a minimum of 200 ns. the reset function requires less than 20 ms to complete. the control logic and register set are initialized and los is set high. the reset pin should be set low for normal operation. rloop1, rloop2 - remote loopback [hardware mode] (plcc pins 7, 6; tqfp pin 63, 62) a remote loopback of the channel is selected when rloop is high. the data received from the line interface at rtip and rring is looped back through the jitter attenuator (if enabled) and retransmitted on ttip and tring. data recovered from rtip and rring continues to be output on rpos/rneg (rdata). data input on tpos/tneg (tdata) is ignored. when the rloop and taos pins are both high, local loopback #1 is invoked along with transmit all ones for the selected channel. the receive input at rtip and rring is ignored. taos1 - transmit all ones select [hardware mode] taos2 - (plcc pins 4, 3; tqfp pins 60, 59) setting taos high causes continuous ones to be transmitted on the line interface at the frequency determined by refclk. when the rloop and taos pins are both high, local loopback #1 is invoked along with transmit all ones for the selected channel. the receive input at rtip and rring is ignored. interface ad7, ad6, ad5, ad4 - address/data bus [host mode - parallel port] ad3, ad2, ad1, ad0 - (plcc pins 63-66, 2-5; tqfp pins 51-54, 58-61) the 8-bit, multiplexed address/data bus. ale (as) - address latch enable (address strobe) [host mode - parallel port] (plcc pin 62; tqfp pin 50) the address present on the address/data bus is latched on the falling edge of this signal. bts - bus type select [host mode - parallel port] (plcc pin 52; tqfp pin 41) this pin controls the function of the rd (ds), ale(as), and wr (r/w ) pins. intel bus timing is selected when bts is low. motorola bus timing is selected when bts is high and the pin function is listed in parenthesis "( )". cs - chip select [host mode] (plcc pin 8; tqfp pin 64) this pin must be low in order to access the serial or parallel port of the device. cs61584a ds261f1 43
cs61584a 44 ds261pp5 ds261pp5 int - receive alarm interrupt [host mode] (plcc pin 7; tqfp pin 63) an interrupt is generated to flag the host processor when a status register changes state. the interrupt is cleared by reading the status register. the logic level for an active interrupt alarm is controlled by the ipol pin. the int pin is an open drain output and must be tied to the appropriate supply through a resistor. ipol - interrupt polarity [host mode, bts = 0] (plcc pin 44; tqfp pin 33) when bts is low (intel bus timing), the active polarity of the int pin is controlled by ipol. an active high interrupt is generated when ipol is high. an active low interrupt is generated when ipol is low. when the bts pin is high, this pin becomes dtack and int is active low. dtack - data acknowledge [host mode - parallel port, bts = 1] (plcc pin 44; tqfp pin 33) when the bts pin is high (motorola bus timing), a low pulse on dtack indicates when the cs61584a has latched the data during a microprocessor write cycle or when the cs61584a has output data to the bus during a microprocessor read cycle. the polarity of the int pin is fixed to active low when the bts pin is high (motorola bus timing). p/s - parallel/serial port selection [host modes] (plcc pin 25; tqfp pin 16) selects the method of communication to the internal register set during host mode operation. serial port communication over the sdi, sdo, and sck pins is selected when p/s is low. parallel port communication over an 8-bit, multiplexed address/data bus is selected when p/s is high. rd (ds) - read input (data strobe) [host mode - parallel port] (plcc pin 6; tqfp pin 62) when the bts pin is low (intel bus timing), a low pulse on rd selects a read operation when the cs pin is low. when the bts pin is high (motorola bus timing), a high pulse on ds performs a read/write operation when the cs pin is low. sad4, sad5 - set chip address [host mode - parallel port] sad6, sad7 - (plcc pins 24, 45, 16, 53; tqfp pins 15, 34, 7, 42) these pins are hard-wired to establish one of 16 possible device addresses to permit a shared parallel bus system architecture. the value is compared with the upper nibble of the address byte ad[7:4] as part of the address decode procedure. sclk - serial clock [host mode - serial port] (plcc pin 6; tqfp pin 62) serial clock used to access the register set. a high or low level can be present on sclk when the device is selected using the cs pin. sdi - serial data input [host mode - serial port] (plcc pin 4; tqfp pin 60) serial data input to the register set. sampled by the device on the rising edge of sclk. sdo - serial data output [host mode - serial port] (plcc pin 5; tqfp pin 61) serial data output from the register set. if spol is low, sdo is valid on the rising edge of sclk. if spol is high, sdo is valid on the falling edge of sclk. the sdo pin goes to a high-impedance state while the serial port is being written or after bit d7 is output on sdo during a read. spol - sdo polarity control [host mode - serial port] (plcc pin 3; tqfp pin 59) controls the polarity of the serial data output sdo. if spol is low, sdo is valid on the rising edge of sclk. if spol is high, sdo is valid on the falling edge of sclk. wr (r/w ) - write input (read/write) [host mode - parallel port] (plcc pin 61; tqfp pin 49) when the bts pin is low (intel bus timing), a low pulse on wr selects a write operation when the cs pin is low. when the bts pin is high (motorola bus timing), a high pulse on r/w selects a read operation and a low pulse on r/w selects a write operation when the cs pin is low. cs61584a 44 ds261f1
cs61584a ds261pp5 45 ds261pp5 status ais1, ais2 - alarm indication signal [host mode] (plcc pins 15, 54; tqfp pins 6, 43) the ais indication goes high when the receiver detects 99.9% ones density in a 5.3 ms period (< 9 zeros in 8192 bits). the ais indication returns low when the receiver detects 3 9 zeros in 8192 bits. bpv1, bpv2 - bipolar violation [host mode] (plcc pins 12, 57; tqfp pins 3, 46) the bpv indication goes high for one rclk bit period when a bipolar violation is detected in the received signal. bipolar violations caused by b8zs (or hdb3) zero substitutions are not flagged by the bpv pin if the coder mode is enabled. the bpv pin also goes high for one rclk bit period on excessive zero events if exz = 1 (control a register, channel 2). in ami mode, the bpv pin goes high when 16 or more zeros are received. in b8zs mode, the bpv pin goes high when 8 or more zeros are received. this functionality is disabled when the device is configured for e1 operation. los1 - loss of signal [hardware mode and host mode - serial port] los2 - (plcc pins 16, 53; tqfp pins 7, 42) the los indication goes high when 175 15 consecutive zeros are received on the line interface, or when the receive (rtip/rring) signal level drop below the receiver sensitivity of the device. the los indication returns low when a minimum 12.5% ones density signal over 175 75 bit periods with no more than 100 consecutive zeros is received. test j-tck - jtag test clock (plcc pin 51; tqfp pin 40) data on pins j-tdi and j-tdo is valid on the rising edge of j-tck. when j-tck is stopped low, all jtag registers remain unchanged. j-tms - jtag test mode select (plcc pin 50; tqfp pin 39) an active high signal on j-tms enables the jtag serial port. this pin has an internal pull-up resistor and may be unconnected to float high or tied low while the jtag interface is not active. j-tdi - jtag test data in (plcc pin 19; tqfp pin 10) jtag data is shifted into the device on this pin. this pin has an internal pull-up resistor. data must be stable on the rising edge of j-tck. j-tdo - jtag test data out (plcc pin 17; tqfp pin 8) jtag data is shifted out of the device on this pin. this pin is active only when jtag testing is in progress. j-tdo will be updated on the falling edge of j-tck. cs61584a ds261f1 45
cs61584a 46 ds261pp5 ds261pp5 12. package dimensions inches millimeters dim min nom max min nom max a --- 0.55 0.063 --- 1.40 1.60 a1 0.002 0.004 0.006 0.05 0.10 0.15 b 0.007 0.008 0.011 0.17 0.20 0.27 d 0.461 0.472 bsc 0.484 11.70 12.0 bsc 12.30 d1 0.390 0.393 bsc 0.398 9.90 10.0 bsc 10.10 e 0.461 0.472 bsc 0.484 11.70 12.0 bsc 12.30 e1 0.390 0.393 bsc 0.398 9.90 10.0 bsc 10.10 e* 0.016 0.020 bsc 0.024 0.40 0.50 bsc 0.60 l 0.018 0.024 0.030 0.45 0.60 0.75 0.000 4 7.000 0.00 4 7.00 * nominal pin pitch is 0.50 mm controlling dimension is mm. jedec designation: ms022 64l lqfp package drawing e1 e d1 d 1 e l b a1 a cs61584a 46 ds261f1
cs61584a ds261pp5 47 ds261pp5 68l plcc package drawing d1 d e1 e d2/e2 b e a1 a inches millimeters dim min nom max min nom max a 0.165 0.1825 0.200 4.191 4.6355 5.08 a1 0.090 0.105 0.130 2.286 2.667 3.302 b 0.013 0.017 0.021 0.3302 0.4318 0.533 d 0.985 0.990 0.995 25.019 25.146 25.273 d1 0.950 0.953 0.958 24.13 24.206 24.333 d2 0.890 0.910 0.930 22.606 23.114 23.622 e 0.985 0.990 0.995 25.019 25.146 25.273 e1 0.950 0.953 0.958 24.13 24.206 24.333 e2 0.890 0.910 0.930 22.606 23.114 23.622 e 0.040 0.050 0.060 1.016 1.270 1.524 jedec #: ms-047 cs61584a ds261f1 47
cs61584a 48 ds261pp5 ds261pp5 13. applications 13.1 line interface figures 27-29 illustrate typical connection diagram for t1 and e1 line interface circuits in hardware, host serial port, and host parallel port modes. ta- ble 13 lists the external components that are re- quired in t1 and e1 applications for both the 5.0 and 3.3 volt devices. in the transmit line interface circuitry, capacitors c1 and c2 provide transmitter return loss. the 0.47 f capacitor in series with the transformer pri- mary prevents output stage imbalances from pro- ducing a dc current through the transformer that might saturate the transformer and result in an out- put level offset. in the receive line interface circuitry, resistors r1- r4 provide receive impedance matching and re- ceiver return loss. the 0.47 f capacitor to ground provides the necessary differential input voltage reference for the receiver. device suffix data rate (mhz) refclk frequency (mhz) transformer turns ratio cable ( w ) r1-r4 ( w ) c1-c2 (pf) 1xclk = 1 1xclk = 0 -il3 and -iq3 (3.3 volts) 1.544 1.544 12.352 1:2 100 12.4 560 2.048 2.048 16.384 75 9.31 2200 120 15.0 560 -il5 and -iq5 (5.0 volts) 1.544 1.544 12.352 1:1.15 100 38.3 220 2.048 2.048 16.384 75 28.7 470 120 45.3 220 table 13. cs61584a external components av+ agnd bgref tv+1 tgnd1 rv+1 rgnd1 dv+ dgnd1:3 0.01 m f tclk1 tpos1 tneg1 rclk1 rpos1 rneg1 tclk2 tpos2 tneg2 rclk2 rpos2 rneg2 framer framer ttip1 tring1 rtip1 rring1 ttip2 tring2 rtip2 rring2 hardware control power supply clock generator channel 2 channel 1 transmit transmit 3 0.1 m f 1 m f + 0.1 m f tv+2 tgnd2 rv+2 rgnd2 22 m f + 0.1 m f 0.1 m f 0.1 m f receive r3 r4 receive r1 r2 t1 t2 t3 t4 r3 4.99k w v cc 0.47 m f 0.47 m f refclk 1xclk reset clke taos[1:2] rloop[1:2] lloop con[0:2]1 con[0:2]2 atten[0:1] c1 c2 0.47 m f 0.47 m f los[1:2] pd[1:2] mode 2 3 22 3 2 2 1:n 1:n 1:n 1:n figure 27. hardware mode configuration cs61584a 48 ds261f1
cs61584a ds261pp5 49 ds261pp5 av+ agnd bgref tv+1 tgnd1 rv+1 rgnd1 dv+ dgnd1:3 0.01 m f tclk1 tpos1 (tdata1) tneg1 (ais1) rclk1 rpos1 (rdata1) rneg1 (bpv1) tclk2 tpos2 (tdata2) tneg2 (ais2) rclk2 rpos2 (rdata2) rneg2 (bpv2) framer framer ttip1 tring1 rtip1 rring1 ttip2 tring2 rtip2 rring2 host control power supply clock generator channel 2 channel 1 transmit transmit 3 0.1 m f 1 m f + 0.1 m f tv+2 tgnd2 rv+2 rgnd2 22 m f + 0.1 m f 0.1 m f 0.1 m f receive r3 r4 receive r1 r2 r3 4.99k w v cc 0.47 m f 0.47 m f refclk 1xclk c1 c2 0.47 m f 0.47 m f ipol p/s cs int sclk sdo sdi spol vcc reset mode los[1:2] 2 t1 t2 t3 t4 1:n 1:n 1:n 1:n ztx[1:2] 2 figure 28. host mode serial port configuration av+ agnd bgref tv+1 tgnd1 rv+1 rgnd1 dv+ dgnd1:3 0.01 m f tclk1 tpos1 (tdata1) tneg1 (ais1) rclk1 rpos1 (rdata1) rneg1 (bpv1) tclk2 tpos2 (tdata2) tneg2 (ais2) rclk2 rpos2 (rdata2) rneg2 (bpv2) framer framer ttip1 tring1 rtip1 rring1 ttip2 tring2 rtip2 rring2 host control power supply clock generator channel 2 channel 1 transmit transmit 3 0.1 m f 1 m f + 0.1 m f tv+2 tgnd2 rv+2 rgnd2 22 m f + 0.1 m f 0.1 m f 0.1 m f receive r3 r4 receive r1 r2 r3 4.99k w v cc 0.47 m f 0.47 m f refclk 1xclk c1 c2 0.47 m f 0.47 m f dtack p/s cs int vcc reset mode rd(ds) ad[0:7] ale(as) wr(r/w) bts sad[4:7] vcc 74 t1 t2 t3 t4 1:n 1:n 1:n 1:n figure 29. host mode parallel port configuration cs61584a ds261f1 49
cs61584a 50 ds261pp5 ds261pp5 13.2 power supply as shown in figure 27, the cs61584a operates from a 3.3 volt or 5.0 volt supply. separate power and ground pins provide internal isolation. the best way to configure the power supplies is to connect all of the supply pins together at the device. the various ground pins must not be more negative than agnd. a 4.99 k w 1% resistor must be connected from bgref to ground to provide an internal cur- rent reference. de-coupling and filtering of the power supplies is crucial for the proper operation of the analog cir- cuits. a capacitor should be connected between each supply and its respective ground. for capaci- tors smaller than 1 f, use mylar or ceramic capac- itors and place them as close as possible to their respective power supply pins. wire-wrap bread boarding of the line interface is not recommended because lead resistance and inductance defeat the function of the de-coupling capacitors. 13.3 quartz crystal specifications when a reference clock signal is not available, a quartz crystal operating at the 8x rate can be con- nected across the refclk and xtalout pins. the crystal must be at-cut and fundamental mode. the minimum specifications are shown in table 14. based on these specifications, quartz crystals suggested for use with the cs61584a are shown in table 15. 13.4 crystal oscillator specifications when a reference clock signal is not available, a cmos crystal oscillator operating at either the 1x or 8x rate can be connected at the refclk pin. the oscillator must have a minimum symmetry of 40-60% and minimum stability of 100 ppm for t1 and e1 applications. based on these specifications, crystal oscillators suggested for use with the parameter min typ max unit t1 parallel resonant frequency - 12.352 - mhz e1 parallel resonant frequency - 16.384 - mhz resonant frequency error (c l = 20 pf) -50 - +50 ppm temperature drift (over system limits) -100 - +100 ppm drive level - - 500 w series resistance - - 50 w shunt capacitance - - 7 pf aging -5 - +5 ppm/yr table 14. quartz crystal specifications manufacturer part number package type m-tron 397-316 ats-49 through-hole 522-372 atsm-49 surface mount saronix srx5769 srx5772 hc-49s through-hole srx5770 srx5773 49smlb surface mount note: frequency tolerances are 32 ppm with a - 40 to +85 c operating temperature range. table 15. suggested quartz crystals manufacturer part number contact number comclok ct31ch (800)333-9825 cts cxo-65hg-5-i (815)786-8411 m-tron mh26tad (800)762-8800 saronix nth250a (800)227-8974 note: frequency tolerances are 32 ppm with a - 40 to +85 c operating temperature range. all are 8-pin dip packages and can be tristated. table 16. suggested crystal oscillators cs61584a 50 ds261f1
cs61584a ds261pp5 51 ds261pp5 13.5 transformers recommended transformer specifications are shown in table 17. based on these specifications, the transformers recommended for use with the cs61584a are listed in table 18. 13.6 designing for at&t 62411 for additional information on the requirements of at&t 62411 and the design of an appropriate sys- tem synchronizer, refer to the crystal semiconduc- tor application notes "at&t 62411 design considerations - jitter and synchronization" and "jitter testing procedures for compliance with at&t 62411." 13.7 line protection secondary protection components can be added to the line interface circuitry to provide lightning surge and ac power-cross immunity. for addition- al information on the different electrical safety standards and specific application circuit recom- mendations, refer to the crystal semiconductor application note "secondary line protection for t1 and e1 line cards." 13.8 loop selection equations the following equations indicate the different states that various inputs have to assume to invoke the various loopback functions available in the de- vice. ...... rloop1 =taos1 .lloop .rloop1 ...... rloop2 =taos2 .lloop .rloop2 ...... lloop11 =lloop2.rloop2.rloop1 + ...... ..............taos1.rloop1 ...... lloop12 =lloop2.rloop2.rloop1 + ...... ..............taos2.rloop2 ...... lloop21 =taos1 .lloop2.(rloop1 + rloop2 ) ...... lloop22 =taos2 .lloop2.(rloop1 + rloop2 ) turns ratio (-il3 and iq3) 1:2 step-up transmit 1:2 step-down receive turns ratio (-il5 and iq5) 1:1.15 step-up transmit 1:1.15 step-down receive primary inductance 1.5 mh min at 772 khz primary leakage inductance 0.3 h max at 772 khz with secondary shorted secondary leakage inductance 0.4 h max at 772 khz interwinding capacitance 18 pf max, primary to secondary et-constant 16 v-s min table 17. transformer specifications cs61584a ds261f1 51
cs61584a 52 ds261pp5 ds261pp5 turns ratio manufacturer part number package type 1:2 (-il3 and -iq3) halo td08-1205a 1.5 kv through-hole, single tg26-1205n1 2 kv surface mount, dual pulse engineering pe-65351 1.5 kv through-hole, single pe-65771 1.5 kv through-hole, single extended temperature pe-65835 3.0 kv through-hole, single extended temperature pe-65761 1.5 kv surface mount, dual pe-65821 1.5 kv surface mount, dual extended temperature pe-65861 1.5 kv surface mount, dual t1016 1.5 kv surface mount, quad t1073 1.5 kv surface mount, octal schott 67129300 1.5 kv through-hole, single extended temperature 67115090 1.5 kv through-hole, dual extended temperature valor st5095 1.5 kv surface mount, dual st5175t 1.5 kv surface mount, quad 1:1.15 (-il5 and -iq5) halo td38-1505a 1.5 kv through-hole, single pulse engineering pe-65388 1.5 kv through-hole, single pe-65770 1.5 kv through-hole, single extended temperature pe-65838 3.0 kv through-hole, single extended temperature pe-68674 1.5 kv surface mount, dual extended temperature pe-65870 1.5 kv surface mount, dual t1016 1.5 kv surface mount, quad t1072 1.5 kv surface mount, octal schott 67124840 1.5 kv through-hole, single extended temperature valor st5112 2.0 kv surface mount, dual st5171t 1.5 kv surface mount, quad table 18. recommended transformers cs61584a 52 ds261f1
cs61584a ds261f1 53 ordering information environmental, manufacturi ng, & handling information * msl (moisture sensitivity level) as specified by ipc/jedec j-std-020. model operating voltage package temperature cs61584a-il3 3.3 v 68-pin plcc -40 to +85 c cs61584a-il5 5.0 v cs61584a-iq3 3.3 v 64-pin lqfp CS61584A-IQ3Z (lead free) cs61584a-iq5 5.0 v cs61584a-iq5z (lead free) model number peak reflow temp msl rating* max floor life cs61584a-il3 225 c 37 days cs61584a-il5 cs61584a-iq3 240 c CS61584A-IQ3Z (lead free) 250 c cs61584a-iq5 240 c cs61584a-iq5z (lead free) 250 c
cs61584a 54 ds261f1 revision history revision date changes pp5 jan 2001 preliminary release f1 sep 2005 updated device ordering info. updated legal notice . added msl data.. contacting cirrus logic support for all product questions and inquiries cont act a cirrus logic sa les representative. to find the one nearest to you go to www.cirrus.com important notice cirrus logic, inc. and its subsidiaries (?cirrus?) believe that the information contained in this document is accurate and reli able. however, the information is subject to change without notice and is provided ?as is? without warranty of any kind (express or implied). customers are advised to ob tain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. all products are sold s ubject to the terms and conditions of sale supplied at the time of order acknowledgment, including those pertaining to warranty, indemnification, and limitation of liabil ity. no responsibility is assumed by cirrus for the use of this information, including use of this information as the basis for manufacture or sale of any items, or for in fringement of patents or other rights of third parties. this document is the property of cirrus and by furnishing this information, cirrus grants no license, express or impli ed under any patents, mask work rights, copyrights, trademarks, trade secrets or other intellectual proper ty rights. cirrus owns the copyrights associated with the inf ormation contained herein and gives con- sent for copies to be made of the information only for use within your organization with respect to cirrus integrated circuits or other products of cirrus. this consent does not extend to other copying such as copying for general di stribution, advertising or promotional purposes, or for creating any work for resale. certain applications usin g semiconductor products may involve potential risks of death, personal injury, or severe prop- erty or environmental damage (?critical applications?). cirrus products are not desi gned, authorized or warranted for use in aircraft systems, military applications, products s urgically implanted into the body, automotive safety or security de- vices, life support products or other critical applic ations. inclusion of cirrus products in such applications is understood to be fully at the customer's risk and cirrus disclaims and makes no warranty, express, statutory or implied, including the implied warranties of merchantab ility and fitness for particular purpose, with regard to any cirrus product that is used in such a manner. if the customer or cu stomer's customer uses or permits the use of cirrus products in critical applica- tions, customer agrees , by such use, to fully indemnify cirrus, its officers, di rectors, employees, distributors and other agents from any and all liability, including attorneys' fees and costs, that may result from or arise in connection with these uses. cirrus logic, cirrus, and the cirrus logic logo designs are trademarks of cirrus logic, inc. all other brand and product names in this document may be trademarks or service marks of their respective owners.

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